?? contadormod8.tan.qmsg
字號(hào):
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLOCK register register FFD:FFD0\|Qu FFD:FFD2\|Qu 500.0 MHz Internal " "Info: Clock \"CLOCK\" Internal fmax is restricted to 500.0 MHz between source register \"FFD:FFD0\|Qu\" and destination register \"FFD:FFD2\|Qu\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.639 ns + Longest register register " "Info: + Longest register to register delay is 0.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FFD:FFD0\|Qu 1 REG LCFF_X31_Y26_N15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y26_N15; Fanout = 4; REG Node = 'FFD:FFD0\|Qu'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FFD:FFD0|Qu } "NODE_NAME" } } { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.256 ns) + CELL(0.228 ns) 0.484 ns FFD:FFD2\|Qu~6 2 COMB LCCOMB_X31_Y26_N18 1 " "Info: 2: + IC(0.256 ns) + CELL(0.228 ns) = 0.484 ns; Loc. = LCCOMB_X31_Y26_N18; Fanout = 1; COMB Node = 'FFD:FFD2\|Qu~6'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.484 ns" { FFD:FFD0|Qu FFD:FFD2|Qu~6 } "NODE_NAME" } } { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.639 ns FFD:FFD2\|Qu 3 REG LCFF_X31_Y26_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.639 ns; Loc. = LCFF_X31_Y26_N19; Fanout = 2; REG Node = 'FFD:FFD2\|Qu'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { FFD:FFD2|Qu~6 FFD:FFD2|Qu } "NODE_NAME" } } { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns ( 59.94 % ) " "Info: Total cell delay = 0.383 ns ( 59.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.256 ns ( 40.06 % ) " "Info: Total interconnect delay = 0.256 ns ( 40.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { FFD:FFD0|Qu FFD:FFD2|Qu~6 FFD:FFD2|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.639 ns" { FFD:FFD0|Qu FFD:FFD2|Qu~6 FFD:FFD2|Qu } { 0.000ns 0.256ns 0.000ns } { 0.000ns 0.228ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK destination 2.493 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK\" to destination register is 2.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLOCK'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "CONTADORMOD8.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/CONTADORMOD8.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'CLOCK~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "CONTADORMOD8.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/CONTADORMOD8.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(0.618 ns) 2.493 ns FFD:FFD2\|Qu 3 REG LCFF_X31_Y26_N19 2 " "Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N19; Fanout = 2; REG Node = 'FFD:FFD2\|Qu'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { CLOCK~clkctrl FFD:FFD2|Qu } "NODE_NAME" } } { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.05 % ) " "Info: Total cell delay = 1.472 ns ( 59.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.021 ns ( 40.95 % ) " "Info: Total interconnect delay = 1.021 ns ( 40.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK CLOCK~clkctrl FFD:FFD2|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { CLOCK CLOCK~combout CLOCK~clkctrl FFD:FFD2|Qu } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 2.493 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK\" to source register is 2.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLOCK'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "CONTADORMOD8.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/CONTADORMOD8.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'CLOCK~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "CONTADORMOD8.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/CONTADORMOD8.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(0.618 ns) 2.493 ns FFD:FFD0\|Qu 3 REG LCFF_X31_Y26_N15 4 " "Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N15; Fanout = 4; REG Node = 'FFD:FFD0\|Qu'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { CLOCK~clkctrl FFD:FFD0|Qu } "NODE_NAME" } } { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.05 % ) " "Info: Total cell delay = 1.472 ns ( 59.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.021 ns ( 40.95 % ) " "Info: Total interconnect delay = 1.021 ns ( 40.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK CLOCK~clkctrl FFD:FFD0|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { CLOCK CLOCK~combout CLOCK~clkctrl FFD:FFD0|Qu } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK CLOCK~clkctrl FFD:FFD2|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { CLOCK CLOCK~combout CLOCK~clkctrl FFD:FFD2|Qu } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK CLOCK~clkctrl FFD:FFD0|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { CLOCK CLOCK~combout CLOCK~clkctrl FFD:FFD0|Qu } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { FFD:FFD0|Qu FFD:FFD2|Qu~6 FFD:FFD2|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.639 ns" { FFD:FFD0|Qu FFD:FFD2|Qu~6 FFD:FFD2|Qu } { 0.000ns 0.256ns 0.000ns } { 0.000ns 0.228ns 0.155ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK CLOCK~clkctrl FFD:FFD2|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { CLOCK CLOCK~combout CLOCK~clkctrl FFD:FFD2|Qu } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK CLOCK~clkctrl FFD:FFD0|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { CLOCK CLOCK~combout CLOCK~clkctrl FFD:FFD0|Qu } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FFD:FFD2|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { FFD:FFD2|Qu } { } { } "" } } { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK Q\[2\] FFD:FFD2\|Qu 5.560 ns register " "Info: tco from clock \"CLOCK\" to destination pin \"Q\[2\]\" through register \"FFD:FFD2\|Qu\" is 5.560 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 2.493 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK\" to source register is 2.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLOCK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLOCK'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "CONTADORMOD8.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/CONTADORMOD8.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'CLOCK~clkctrl'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "CONTADORMOD8.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/CONTADORMOD8.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(0.618 ns) 2.493 ns FFD:FFD2\|Qu 3 REG LCFF_X31_Y26_N19 2 " "Info: 3: + IC(0.678 ns) + CELL(0.618 ns) = 2.493 ns; Loc. = LCFF_X31_Y26_N19; Fanout = 2; REG Node = 'FFD:FFD2\|Qu'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { CLOCK~clkctrl FFD:FFD2|Qu } "NODE_NAME" } } { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.05 % ) " "Info: Total cell delay = 1.472 ns ( 59.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.021 ns ( 40.95 % ) " "Info: Total interconnect delay = 1.021 ns ( 40.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK CLOCK~clkctrl FFD:FFD2|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { CLOCK CLOCK~combout CLOCK~clkctrl FFD:FFD2|Qu } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.973 ns + Longest register pin " "Info: + Longest register to pin delay is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FFD:FFD2\|Qu 1 REG LCFF_X31_Y26_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y26_N19; Fanout = 2; REG Node = 'FFD:FFD2\|Qu'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FFD:FFD2|Qu } "NODE_NAME" } } { "FFD.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/FFD.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(2.154 ns) 2.973 ns Q\[2\] 2 PIN PIN_C1 0 " "Info: 2: + IC(0.819 ns) + CELL(2.154 ns) = 2.973 ns; Loc. = PIN_C1; Fanout = 0; PIN Node = 'Q\[2\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { FFD:FFD2|Qu Q[2] } "NODE_NAME" } } { "CONTADORMOD8.vhd" "" { Text "C:/Documents and Settings/Alejandro Aguilar/Desktop/Tarea1/ESTRUCTURAL/CONTADORMOD8.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.154 ns ( 72.45 % ) " "Info: Total cell delay = 2.154 ns ( 72.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 27.55 % ) " "Info: Total interconnect delay = 0.819 ns ( 27.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { FFD:FFD2|Qu Q[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { FFD:FFD2|Qu Q[2] } { 0.000ns 0.819ns } { 0.000ns 2.154ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK CLOCK~clkctrl FFD:FFD2|Qu } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.493 ns" { CLOCK CLOCK~combout CLOCK~clkctrl FFD:FFD2|Qu } { 0.000ns 0.000ns 0.343ns 0.678ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { FFD:FFD2|Qu Q[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { FFD:FFD2|Qu Q[2] } { 0.000ns 0.819ns } { 0.000ns 2.154ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 25 18:02:47 2007 " "Info: Processing ended: Tue Sep 25 18:02:47 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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