module         sha256_sha512_cal  (                            clk,                                rst_n, 			    sha256_sw_rst,			    sha512_sw_rst,			    sha256_start,			    sha512_start,                                                       reg_a,                            reg_b,                            reg_c,                            reg_d,                            reg_e,                            reg_f,                            reg_g,                            reg_h,                                                        			                                wt_data_out,                            wt_dataout_en,                           // output                                 wt_request      ,                            a_temp          ,                                                                             b_temp          ,                                                            c_temp          ,                                                                 d_temp          ,                                                                 e_temp          ,                            f_temp          ,                                                                 g_temp          ,                                                                 h_temp          ,			                                cal_ready,			    sha256_ready,			    sha512_ready    			    );                                                                                                                      input  clk;          input  rst_n;          input  sha256_sw_rst;input  sha512_sw_rst;input  sha256_start;input  sha512_start;input[63:0]                 reg_a      ;           //data from a reg( A --> a)input[63:0]                 reg_b      ;           //data from b reg( B --> b)input[63:0]                 reg_c      ;           //data from c reg( C --> c) input[63:0]                 reg_d      ;           //data from d reg( D --> d) input[63:0]                 reg_e      ;           //data from e reg( E --> e)   input[63:0]                 reg_f      ;    //temp store the "C", 1, for transfer to "c" 2, for final 32bit adderinput[63:0]                 reg_g      ;    //temp store the "D", 1, for transfer to "d" 2, for final 32bit adderinput[63:0]                 reg_h      ;    //temp store the "E", 1, for transfer to "e" 2, for final 32bit adder     input[63:0]                 wt_data_out     ;           //the data from wt shift reginput                       wt_dataout_en   ;           //enable the wt data output                      wt_request      ;           //request the wt dataoutput[63:0]                a_temp          ;           //a out to adderoutput[63:0]                b_temp          ;           //a out to adder  output[63:0]                c_temp          ;           //a out to adder  output[63:0]                d_temp          ;           //a out to adder  output[63:0]                e_temp          ;           //a out to adder output[63:0]                f_temp          ;           //a out to adder  output[63:0]                g_temp          ;           //a out to adder  output[63:0]                h_temp          ;           //a out to adder output  cal_ready      ;output  sha256_ready;output  sha512_ready;reg                         wt_request      ;                            reg[63:0]                   a_temp          ;reg[63:0]                   b_temp          ;reg[63:0]                   c_temp          ;reg[63:0]                   d_temp          ;reg[63:0]                   e_temp          ;reg[63:0]                   f_temp          ;reg[63:0]                   g_temp          ;reg[63:0]                   h_temp          ;wire  cal_ready      ;reg   sha256_ready;reg   sha512_ready;                 reg[6:0]                    cal_t          ;        // the times of calculating, it is 80 times;wire [63:0] dat1;wire [63:0] dat2;wire start_pulse;reg start_delay;always @ (posedge clk or negedge rst_n)begin  if(!rst_n) start_delay <= 1'b0;  else if(sha256_sw_rst|sha512_sw_rst) start_delay <= 1'b0;  else start_delay <= (sha256_start|sha512_start);endassign start_pulse = (sha256_start|sha512_start)&~start_delay;always@(posedge clk or negedge rst_n)begin    if(!rst_n)           cal_t   <=  7'b0 ;    else if(sha256_sw_rst|sha512_sw_rst)           cal_t   <=  7'b0 ;    else if((sha256_start|sha512_start) && wt_dataout_en)           cal_t   <= cal_t + 1'b1;    else if(cal_ready)           cal_t   <=  7'b0;end           //assign       cal_busy  =  wt_dataout_en   ;           always@(posedge clk or negedge rst_n)begin    if(!rst_n)         wt_request   <= 1'b0;    else if(sha256_sw_rst|sha512_sw_rst)         wt_request   <= 1'b0;    else if(~(sha256_ready|sha512_ready)&      ( (sha512_start&& cal_t <=7'd77)      ||(sha256_start && cal_t <=7'd61)))         wt_request   <= 1'b1;    else          wt_request   <= 1'b0;endalways@(posedge clk or negedge rst_n)begin    if(!rst_n)begin      sha256_ready <= 1'b0;      sha512_ready <= 1'b0;    end             else if(sha256_sw_rst|sha512_sw_rst)begin         sha256_ready <= 1'b0;         sha512_ready <= 1'b0;      end    else begin      sha256_ready <= cal_ready&sha256_start;      sha512_ready <= cal_ready&sha512_start;    end      end                   assign  cal_ready = (cal_t == 7'd80 && sha512_start)|| (cal_t==7'd64 && sha256_start) ;          always@(posedge clk or negedge rst_n)begin     if(!rst_n)          begin              a_temp  <= 64'd0;              b_temp  <= 64'd0;              c_temp  <= 64'd0;              d_temp  <= 64'd0;              e_temp  <= 64'd0;              f_temp  <= 64'd0;              g_temp  <= 64'd0;              h_temp  <= 64'd0;          end         else if(sha256_sw_rst|sha512_sw_rst)          begin              a_temp  <= 64'd0;              b_temp  <= 64'd0;              c_temp  <= 64'd0;              d_temp  <= 64'd0;              e_temp  <= 64'd0;              f_temp  <= 64'd0;              g_temp  <= 64'd0;              h_temp  <= 64'd0;          end         else  if(start_pulse)                               //load "A,,,E" --> "a,,,e"          begin                  a_temp  <=  reg_a;                  b_temp  <=  reg_b;                  c_temp  <=  reg_c;                  d_temp  <=  reg_d;                  e_temp  <=  reg_e;                  f_temp  <=  reg_f;                  g_temp  <=  reg_g;                  h_temp  <=  reg_h;           end     else if(wt_dataout_en)                   begin                   a_temp  <=  dat1 + dat2	;                   b_temp  <=  a_temp        	;                   c_temp  <=  b_temp		;                   d_temp  <=  c_temp        	;                   e_temp  <=  d_temp + dat1 	;                    f_temp  <=  e_temp		;                   g_temp  <=  f_temp        	;                   h_temp  <=  g_temp        	;           endend           wire [63:0] kt;sha256_sha512_k  u_sha256_sha512_k(.sha256_start(sha256_start),.cal_t(cal_t),.kt(kt));wire [31:0] dat1_256_1 = h_temp[63:32];wire [63:0] dat1_256_2 = sha256_rot1(e_temp);wire [63:0] dat1_256_3 = ch(e_temp,f_temp,g_temp);wire [31:0] dat1_256_4 = kt[63:32];wire [31:0] dat1_256_5 = wt_data_out[63:32];wire [31:0] dat1_256 =  dat1_256_1 + dat1_256_2[63:32] + dat1_256_3[63:32] + dat1_256_4 + dat1_256_5;wire [63:0] dat1_256_f = {dat1_256,32'd0};wire [63:0] dat2_256_1 = sha256_rot0(a_temp);wire [63:0] dat2_256_2 =  maj(a_temp,b_temp,c_temp);wire [31:0] dat2_256 = dat2_256_1[63:32] + dat2_256_2[63:32];assign dat1 = sha256_start ? ({dat1_256,32'd0}) : (h_temp + sha512_rot1(e_temp) + ch(e_temp,f_temp,g_temp) + kt + wt_data_out);assign dat2 = sha256_start ? ({dat2_256,32'd0}) : (sha512_rot0(a_temp) + maj(a_temp,b_temp,c_temp));             // -------------------------------------------// 	-- function realize --// -------------------------------------------function [63:0] ch;input [63:0] x;input [63:0] y;input [63:0] z;reg [63:0] tmp1,tmp2;begin	tmp1 = x&y;	tmp2 = (~x)&z;	ch = tmp1^tmp2;endendfunction//		--------------function [63:0] maj;input [63:0] x;input [63:0] y;input [63:0] z;begin	maj = (x&y)^(y&z)^(x&z);endendfunction//		--------------function [63:0] sha512_rot0;input [63:0] x;reg [63:0] rot28;reg [63:0] rot34;reg [63:0] rot39;begin	rot28 = {x[27:0],x[63:28]};	rot34 = {x[33:0],x[63:34]};	rot39 = {x[38:0],x[63:39]};	sha512_rot0 = rot28^rot34^rot39;endendfunction//		--------------function [63:0] sha512_rot1;input [63:0] x;reg [63:0] rot14;reg [63:0] rot18;reg [63:0] rot41;begin	rot14 = {x[13:0],x[63:14]};	rot18 = {x[17:0],x[63:18]};	rot41 = {x[40:0],x[63:41]};	sha512_rot1 = rot14^rot18^rot41;endendfunction//		--------------function [63:0] sha256_rot0;input [63:0] x;reg [31:0] rot2;reg [31:0] rot13;reg [31:0] rot22;reg [31:0] y;begin	rot2 =  {x[33:32],x[63:34]};	rot13 = {x[44:32],x[63:45]};	rot22 = {x[53:32],x[63:54]};	y = rot2^rot13^rot22;	sha256_rot0 = {y,32'd0};endendfunction//		--------------function [63:0] sha256_rot1;input [63:0] x;reg [31:0] rot6;reg [31:0] rot11;reg [31:0] rot25;reg [31:0] y;begin	rot6  = {x[37:32],x[63:38]};	rot11 = {x[42:32],x[63:43]};	rot25 = {x[56:32],x[63:57]};	y = rot6^rot11^rot25;	sha256_rot1 = {y,32'd0};endendfunction          endmodule