{ "Info" "ITDB_TSU_RESULT" "control_wr_rd_for_SRAM:BLOCK4\|current_state.Wait_buffer_High KEY\[0\] CLOCK_50 3.590 ns register " "Info: tsu for register \"control_wr_rd_for_SRAM:BLOCK4\|current_state.Wait_buffer_High\" (data pin = \"KEY\[0\]\", clock pin = \"CLOCK_50\") is 3.590 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.929 ns + Longest pin register " "Info: + Longest pin to register delay is 7.929 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 PIN PIN_G26 448 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 448; PIN Node = 'KEY\[0\]'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.557 ns) + CELL(0.510 ns) 7.929 ns control_wr_rd_for_SRAM:BLOCK4\|current_state.Wait_buffer_High 2 REG LCFF_X28_Y11_N19 3 " "Info: 2: + IC(6.557 ns) + CELL(0.510 ns) = 7.929 ns; Loc. = LCFF_X28_Y11_N19; Fanout = 3; REG Node = 'control_wr_rd_for_SRAM:BLOCK4\|current_state.Wait_buffer_High'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "7.067 ns" { KEY[0] control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.372 ns ( 17.30 % ) " "Info: Total cell delay = 1.372 ns ( 17.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.557 ns ( 82.70 % ) " "Info: Total interconnect delay = 6.557 ns ( 82.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "7.929 ns" { KEY[0] control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "7.929 ns" { KEY[0] KEY[0]~combout control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } { 0.000ns 0.000ns 6.557ns } { 0.000ns 0.862ns 0.510ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 4.303 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 4.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.117 ns clock 2 REG LCFF_X1_Y18_N23 3 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.117 ns; Loc. = LCFF_X1_Y18_N23; Fanout = 3; REG Node = 'clock'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.118 ns" { CLOCK_50 clock } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.000 ns) 2.751 ns clock~clkctrl 3 COMB CLKCTRL_G1 1185 " "Info: 3: + IC(0.634 ns) + CELL(0.000 ns) = 2.751 ns; Loc. = CLKCTRL_G1; Fanout = 1185; COMB Node = 'clock~clkctrl'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.634 ns" { clock clock~clkctrl } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.537 ns) 4.303 ns control_wr_rd_for_SRAM:BLOCK4\|current_state.Wait_buffer_High 4 REG LCFF_X28_Y11_N19 3 " "Info: 4: + IC(1.015 ns) + CELL(0.537 ns) = 4.303 ns; Loc. = LCFF_X28_Y11_N19; Fanout = 3; REG Node = 'control_wr_rd_for_SRAM:BLOCK4\|current_state.Wait_buffer_High'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.552 ns" { clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 53.99 % ) " "Info: Total cell delay = 2.323 ns ( 53.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.980 ns ( 46.01 % ) " "Info: Total interconnect delay = 1.980 ns ( 46.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.303 ns" { CLOCK_50 clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.303 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } { 0.000ns 0.000ns 0.331ns 0.634ns 1.015ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "7.929 ns" { KEY[0] control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "7.929 ns" { KEY[0] KEY[0]~combout control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } { 0.000ns 0.000ns 6.557ns } { 0.000ns 0.862ns 0.510ns } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.303 ns" { CLOCK_50 clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.303 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|current_state.Wait_buffer_High } { 0.000ns 0.000ns 0.331ns 0.634ns 1.015ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 VGA_R\[9\] vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a7 14.809 ns memory " "Info: tco from clock \"CLOCK_50\" to destination pin \"VGA_R\[9\]\" through memory \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a7\" is 14.809 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 4.332 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK_50\" to source memory is 4.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.117 ns clock 2 REG LCFF_X1_Y18_N23 3 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.117 ns; Loc. = LCFF_X1_Y18_N23; Fanout = 3; REG Node = 'clock'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.118 ns" { CLOCK_50 clock } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.000 ns) 2.751 ns clock~clkctrl 3 COMB CLKCTRL_G1 1185 " "Info: 3: + IC(0.634 ns) + CELL(0.000 ns) = 2.751 ns; Loc. = CLKCTRL_G1; Fanout = 1185; COMB Node = 'clock~clkctrl'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.634 ns" { clock clock~clkctrl } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.635 ns) 4.332 ns vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a7 4 MEM M4K_X13_Y9 1 " "Info: 4: + IC(0.946 ns) + CELL(0.635 ns) = 4.332 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a7'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.581 ns" { clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 } "NODE_NAME" } } { "db/altsyncram_4qc1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 193 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.421 ns ( 55.89 % ) " "Info: Total cell delay = 2.421 ns ( 55.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.911 ns ( 44.11 % ) " "Info: Total interconnect delay = 1.911 ns ( 44.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.332 ns" { CLOCK_50 clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.332 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 } { 0.000ns 0.000ns 0.331ns 0.634ns 0.946ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.635ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_4qc1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 193 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.268 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.088 ns) 0.088 ns vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a7 1 MEM M4K_X13_Y9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X13_Y9; Fanout = 1; MEM Node = 'vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a7'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 } "NODE_NAME" } } { "db/altsyncram_4qc1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 193 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.448 ns) + CELL(0.275 ns) 2.811 ns vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|mux_kib:mux2\|result_node\[7\]~366 2 COMB LCCOMB_X25_Y18_N16 1 " "Info: 2: + IC(2.448 ns) + CELL(0.275 ns) = 2.811 ns; Loc. = LCCOMB_X25_Y18_N16; Fanout = 1; COMB Node = 'vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|mux_kib:mux2\|result_node\[7\]~366'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "2.723 ns" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~366 } "NODE_NAME" } } { "db/mux_kib.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/mux_kib.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.150 ns) 3.970 ns vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|mux_kib:mux2\|result_node\[7\]~367 3 COMB LCCOMB_X29_Y14_N2 1 " "Info: 3: + IC(1.009 ns) + CELL(0.150 ns) = 3.970 ns; Loc. = LCCOMB_X29_Y14_N2; Fanout = 1; COMB Node = 'vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|mux_kib:mux2\|result_node\[7\]~367'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.159 ns" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~366 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~367 } "NODE_NAME" } } { "db/mux_kib.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/mux_kib.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.236 ns) + CELL(0.150 ns) 4.356 ns vga_controller:BLOCK2\|vga_r\[9\]~111 4 COMB LCCOMB_X29_Y14_N0 3 " "Info: 4: + IC(0.236 ns) + CELL(0.150 ns) = 4.356 ns; Loc. = LCCOMB_X29_Y14_N0; Fanout = 3; COMB Node = 'vga_controller:BLOCK2\|vga_r\[9\]~111'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.386 ns" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~367 vga_controller:BLOCK2|vga_r[9]~111 } "NODE_NAME" } } { "vga_controller.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_controller.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.144 ns) + CELL(2.768 ns) 10.268 ns VGA_R\[9\] 5 PIN PIN_E10 0 " "Info: 5: + IC(3.144 ns) + CELL(2.768 ns) = 10.268 ns; Loc. = PIN_E10; Fanout = 0; PIN Node = 'VGA_R\[9\]'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "5.912 ns" { vga_controller:BLOCK2|vga_r[9]~111 VGA_R[9] } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.431 ns ( 33.41 % ) " "Info: Total cell delay = 3.431 ns ( 33.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.837 ns ( 66.59 % ) " "Info: Total interconnect delay = 6.837 ns ( 66.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "10.268 ns" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~366 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~367 vga_controller:BLOCK2|vga_r[9]~111 VGA_R[9] } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "10.268 ns" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~366 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~367 vga_controller:BLOCK2|vga_r[9]~111 VGA_R[9] } { 0.000ns 2.448ns 1.009ns 0.236ns 3.144ns } { 0.088ns 0.275ns 0.150ns 0.150ns 2.768ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.332 ns" { CLOCK_50 clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.332 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 } { 0.000ns 0.000ns 0.331ns 0.634ns 0.946ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.635ns } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "10.268 ns" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~366 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~367 vga_controller:BLOCK2|vga_r[9]~111 VGA_R[9] } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "10.268 ns" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a7 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~366 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2|result_node[7]~367 vga_controller:BLOCK2|vga_r[9]~111 VGA_R[9] } { 0.000ns 2.448ns 1.009ns 0.236ns 3.144ns } { 0.088ns 0.275ns 0.150ns 0.150ns 2.768ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM SW\[0\] CLOCK_50 -1.557 ns register " "Info: th for register \"control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM\" (data pin = \"SW\[0\]\", clock pin = \"CLOCK_50\") is -1.557 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 4.322 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 4.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.117 ns clock 2 REG LCFF_X1_Y18_N23 3 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.117 ns; Loc. = LCFF_X1_Y18_N23; Fanout = 3; REG Node = 'clock'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.118 ns" { CLOCK_50 clock } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.000 ns) 2.751 ns clock~clkctrl 3 COMB CLKCTRL_G1 1185 " "Info: 3: + IC(0.634 ns) + CELL(0.000 ns) = 2.751 ns; Loc. = CLKCTRL_G1; Fanout = 1185; COMB Node = 'clock~clkctrl'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.634 ns" { clock clock~clkctrl } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.537 ns) 4.322 ns control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM 4 REG LCFF_X28_Y7_N9 5 " "Info: 4: + IC(1.034 ns) + CELL(0.537 ns) = 4.322 ns; Loc. = LCFF_X28_Y7_N9; Fanout = 5; REG Node = 'control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.571 ns" { clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 53.75 % ) " "Info: Total cell delay = 2.323 ns ( 53.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.999 ns ( 46.25 % ) " "Info: Total interconnect delay = 1.999 ns ( 46.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.322 ns" { CLOCK_50 clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.322 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } { 0.000ns 0.000ns 0.331ns 0.634ns 1.034ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 48 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.145 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.145 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[0\] 1 PIN PIN_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 1; PIN Node = 'SW\[0\]'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.340 ns) + CELL(0.438 ns) 3.777 ns control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM~328 2 COMB LCCOMB_X29_Y5_N30 1 " "Info: 2: + IC(2.340 ns) + CELL(0.438 ns) = 3.777 ns; Loc. = LCCOMB_X29_Y5_N30; Fanout = 1; COMB Node = 'control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM~328'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "2.778 ns" { SW[0] control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~328 } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.420 ns) 4.451 ns control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM~329 3 COMB LCCOMB_X29_Y5_N20 1 " "Info: 3: + IC(0.254 ns) + CELL(0.420 ns) = 4.451 ns; Loc. = LCCOMB_X29_Y5_N20; Fanout = 1; COMB Node = 'control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM~329'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.674 ns" { control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~328 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~329 } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.436 ns) 5.154 ns control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM~330 4 COMB LCCOMB_X29_Y5_N22 1 " "Info: 4: + IC(0.267 ns) + CELL(0.436 ns) = 5.154 ns; Loc. = LCCOMB_X29_Y5_N22; Fanout = 1; COMB Node = 'control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM~330'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.703 ns" { control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~329 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~330 } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.758 ns) + CELL(0.149 ns) 6.061 ns control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM~331 5 COMB LCCOMB_X28_Y7_N8 1 " "Info: 5: + IC(0.758 ns) + CELL(0.149 ns) = 6.061 ns; Loc. = LCCOMB_X28_Y7_N8; Fanout = 1; COMB Node = 'control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM~331'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.907 ns" { control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~330 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~331 } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.145 ns control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM 6 REG LCFF_X28_Y7_N9 5 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 6.145 ns; Loc. = LCFF_X28_Y7_N9; Fanout = 5; REG Node = 'control_wr_rd_for_SRAM:BLOCK4\|enable_do_read_on_SRAM'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~331 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.526 ns ( 41.11 % ) " "Info: Total cell delay = 2.526 ns ( 41.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.619 ns ( 58.89 % ) " "Info: Total interconnect delay = 3.619 ns ( 58.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "6.145 ns" { SW[0] control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~328 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~329 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~330 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~331 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "6.145 ns" { SW[0] SW[0]~combout control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~328 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~329 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~330 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~331 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } { 0.000ns 0.000ns 2.340ns 0.254ns 0.267ns 0.758ns 0.000ns } { 0.000ns 0.999ns 0.438ns 0.420ns 0.436ns 0.149ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.322 ns" { CLOCK_50 clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.322 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } { 0.000ns 0.000ns 0.331ns 0.634ns 1.034ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "6.145 ns" { SW[0] control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~328 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~329 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~330 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~331 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "6.145 ns" { SW[0] SW[0]~combout control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~328 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~329 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~330 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM~331 control_wr_rd_for_SRAM:BLOCK4|enable_do_read_on_SRAM } { 0.000ns 0.000ns 2.340ns 0.254ns 0.267ns 0.758ns 0.000ns } { 0.000ns 0.999ns 0.438ns 0.420ns 0.436ns 0.149ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}