?? k401init.s
字號:
;; ******************************************************
;; * NAME : K401INIT.S *
;; * Date : 1.NOV.1999 *
;; * Author : yong-hyeon Kim *
;; * E-mail : telecom2@sec.samsung.com *
;; * Description: *
;; * C start up codes *
;; * Configure memory, Initialize ISR ,stacks *
;; * Initialize C-variables *
;; * Fill zeros into zero-initialized C-variables *
;; ******************************************************
GET ..\include\option.a
;; Memory Area for SMDK40100 (buswidth = 16)
;; nCS0 128K 16bit ROM (0x0 ~ 0x1ffff)
;; nCS1 256K 16bit SRAM (0x100000 ~ 0x17ffff)
;; GCS6 8M 16bit DRAM or SDRAM (0x1000000~0x1ffffff)
;; SDRAM (64 Mbyte) Configuration
;; ---------------------------- 0x2000000
;; | Reserved Area |
;; |----------------------------| 0x1ffffac
;; | Interrupt Handler |
;; |----------------------------| 0x1ffff20
;; | Exception Handler |
;; |----------------------------| 0x1ffff00
;; | Stack Area |
;; |----------------------------| 0x1fffa00
;; | |
;; | Data Area |
;; | |
;; |----------------------------| 0x1ff0000
;; | |
;; | Code Area |
;; | |
;; ---------------------------- 0x1000000
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
IMPORT Main
AREA Init,CODE,READONLY
ENTRY
;; --------------------------------------------------------------------------------------------------
;; Booting from address 0
;; Setup Exception Vectors
;; --------------------------------------------------------------------------------------------------
b ResetHandler ;for debug
b HandlerUndef ;handlerUndef
b HandlerSWI ;SWI interrupt handler
b HandlerPabort ;handlerPAbort
b HandlerDabort ;handlerDAbort
b . ;handlerReserved
b HandlerIRQ
;b HandlerFIQ ; Remake to save FIQ access time......
;; --------------------------------------------------------------------------------------------------
;; Exception Processing
;; --------------------------------------------------------------------------------------------------
;; Fetch the hander entry address from the exception handler table located
;; in DRAM locations 0x1ffff00 to 0x1ffff20, and then deliver the address to the "PC"
;; in order to pass control to the corresponding exception handler
;; --------------------------------------------------------------------------------------------------
HandlerFIQ
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleFIQ
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerIRQ ;This isn't used. IsrIRQ is used instead.
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleIRQ
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerUndef
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleUndef
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerSWI
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleSWI
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerDabort
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandleDabort
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
HandlerPabort
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=HandlePabort
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
IsrIRQ
sub sp,sp,#4 ;reserved for PC
stmfd sp!,{r8-r10}
ldr r8,=INTMOD
ldmia r8,{r8-r10} ;r8=IntMode,r9=IntPend,r10=IntMask
mvn r8,r8
and r8,r8,r9
and r8,r8,r10 ;r8 has IRQ,Unmasked,Pending bit
mov r9,#0
0 movs r8,r8,lsr #1
bcs %F1
add r9,r9,#4
b %B0
1 ldr r10,=HandleEINT0 ;IntVectorTable must not be used.
add r10,r10,r9
ldr r10,[r10]
str r10,[sp,#12];
ldmfd sp!,{r8-r10,pc}
ldr pc, =EnterPWDN
;; --------------------------------------------------------------------------------------------------
;; The Reset Entry Point
;; --------------------------------------------------------------------------------------------------
ResetHandler
;; Setup the SYSCFG register
;; - Special register base address(Reset value): 0x7ff0000
;; - Memory type=SDRAM(Bank6), ROM/SRAM(Bank7)
;; SFR Start Address=0x3ff0000, Cache On, Cache size=4KB, Write Buffer Off, Stall Disable
[ DRAMTYPE="SDRAM"
ldr r0, =0x7ff1000
ldr r1, =0xdfff0
; ldr r1, SyscfgDataSdram
str r1, [r0]
| ;; "DRAM"
ldr r0, =0x7ff100
ldr r1 SyscfgDataEdoDram
str r1, [r0]
]
;; Disable watch-dog timer
ldr r0, =BTCON
ldr r1, =WDT_DISABLE
strh r1, [r0]
;; I/O port Configuration
;; Port 0 Configuration
;; P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
;; EINT0 OUT OUT OUT OUT OUT OUT OUT
;; 00 01 01 1 1 1 1 1 (xxxx x000 1011 1111)
;; UP (1000 0000)
ldr r1, =PCON0
ldr r0, =0x00bf
strh r0, [r1]
ldr r1, =PUR0
ldr r0, =0x80
strb r0, [r1]
;; Port 1 Configuration
;; P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
;; IN IN IN IN IN A18 A17 A16
;; 0 0 0 0 0 1 1 1
;; 0 0 0 0 0 x x x (0000 0111 0000 0000)
;; DOWN DOWN DOWN DOWN DOWN (1111 1000)
ldr r1, =PCON1
ldr r0, =0x0700
strh r0, [r1]
ldr r1, =PDR1
ldr r0, =0xf8
strb r0, [r1]
;; Port 2 Configuration
;; P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
;; EINT1 IN nRAS0 OUT OUT OUT OUT nCS1
;; 00 00 10 01 01 01 01 10 (0000 1001 0101 0110)
;; UP UP (1100 0000)
ldr r1, =PCON2
ldr r0, =0x0956
strh r0, [r1]
ldr r1, =PUR2
ldr r0, =0xc0
strb r0, [r1]
;; Port 3 Configuration
;; P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
;; EINT2 SCLK SCKE nWE nCAS1 nCAS0 nWBE1 nWBE0
;; 00 10 10 10 10 10 10 10 (0010 1010 1010 1010)
;; DOWN (1000 0000)
ldr r1, =PCON3
ldr r0, =0x2aaa
strh r0, [r1]
ldr r1, =PUR3
ldr r0, =0x80
strb r0, [r1]
;; Port 4 Configuration
;; P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
;; D15 D14 D13 D12 D11 D10 D9 D8
;; 11 11 11 11 11 11 11 11 (1111 1111 1111 1111)
;; (0000 0000)
ldr r1, =PCON4
ldr r0, =0xffff
strh r0, [r1]
ldr r1, =PDR4
ldr r0, =0x0
strb r0, [r1]
;; Port 5 Configuration
;; P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
;; UTXD URXD IN IN IN IN IN IN
;; 101 00 00 00 00 00 00 00 (xxxx xxxx xxxx xxx1 0100 0000 0000 0000)
;; UP UP UP UP UP UP (0011 1111)
ldr r1, =PCON5
ldr r0, =0x14000
str r0, [r1]
ldr r1, =PUR5
ldr r0, =0x3f
strb r0, [r1]
;; Port 6 Configuration
;; P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0
;; EINT3 STXD1 IN SRXD1 IN STXD0 IN SRXD0
;; 0 101 000 00 00 101 000 00 (xxxx xxxx xxxx x010 1000 0000 1010 0000)
;; UP UP UP UP UP UP (1011 1011)
ldr r1, =PCON6
ldr r0, =0x280a0
str r0, [r1]
ldr r1, =PUR6
ldr r0, =0xbb
strb r0, [r1]
;; Port 7 Configuration
;; HNS LNS RTO P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0
;; T0 T0 GIOP IN IN IN IN IN IN IN IN
;; 0 0 00 0 0 0 0 0 0 0 0 (xxxx 0000 0000 0000)
;; UP UP UP UP UP UP UP UP (1111 1111)
ldr r1, =PCON7
ldr r0, =0x0
strh r0, [r1]
ldr r1, =PUR7
ldr r0, =0xff
strb r0, [r1]
;; Port 8 Configuration
;; P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0
;; IN IN IN IN IN IN IN IN
;; 0 0 0 0 0 0 0 0 (0000 0000)
;; UP UP UP UP UP UP UP UP (1111 1111)
ldr r1, =PCON8
ldr r0, =0x0
strb r0, [r1]
ldr r1, =PUR8
ldr r0, =0xff
strb r0, [r1]
;; System Control configuration
;; - Grobal interrupt mask, System Clock=MCLK, Normal operation
ldr r0, =SYSCON
mov r1, #0x10
strb r1, [r0]
;; All Interrupt Disable
ldr r0, =INTMOD
mov r1, #0x0 ; All IRQ
str r1, [r0]
ldr r0, =INTMSK
mov r1, #0x0
str r1, [r0] ; All disable
;; Configuration memory allocation
;; This operation must be performed immediately
ldr r0, =SMRDATA ; Load address of area 'SMRDATA'
ldmia r0, {r1-r9} ; Load each word value of 'SMRDATA'
ldr r0, =MEMCON0 ; MEMBANK0 offset : 0x2000
stmia r0, {r1-r9} ; Store each 'SMRDATA' value to the system manager registers
ldr sp, =SVCStack
bl InitStacks
;;
ldr r0, =HandleIRQ
ldr r1, =IsrIRQ
str r1, [r0]
;; --------------------------------------------------------------------------------------------------
;; Initialization for C source program
;; --------------------------------------------------------------------------------------------------
;; Initialize memory required for C code
;; - RAM initialization
;; - Copy all read/write data from Assembler & C code to the read/write area
;; - Copy Zero initialized data from C code to the read/write area(for example, global variable)
;; --------------------------------------------------------------------------------------------------
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base| ; Zero init base => top of initialized data
CMP r0, r1 ; Check that they are different
BEQ %F1
0
CMP r1, r3
LDRCC r2, [r0], #4
STRCC r2, [r1], #4
BCC %B0
1
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
2
CMP r3, r1
STRCC r2, [r3], #4
BCC %B2
BL Main
B .
;; --------------------------------------------------------------------------------------------------
;; Initialize the SPand SPSR for each mode as follows:
;; - Corresponding stack entry => SP(Stack Pointer)
;; - User mode with I/F clear => SPSR (Return Mode)
;; Don't use DRAM,such as stmfd,ldmfd......
;; SVCstack is initialized before
;; --------------------------------------------------------------------------------------------------
InitStacks
mrs r0, cpsr
bic r0, r0, #MODEMASK
orr r1, r0, #UNDEFMODE|NOINT
msr cpsr_cxsf, r1 ;UndefMode
ldr sp, =UndefStack
orr r1, r0, #ABORTMODE|NOINT
msr cpsr_cxsf, r1 ;AbortMode
ldr sp, =AbortStack
orr r1, r0, #IRQMODE|NOINT
msr cpsr_cxsf, r1 ;IRQMode
ldr sp, =IRQStack
orr r1, r0, #FIQMODE|NOINT
msr cpsr_cxsf, r1 ;FIQMode
ldr sp, =FIQStack
bic r0, r0, #MODEMASK|NOINT
orr r1, r0, #SVCMODE
msr cpsr_cxsf, r1 ;SVCMode
ldr sp, =SVCStack
;USER mode is not initialized.
mov pc, lr ;The LR register may be not valid for the mode changes.
LTORG
;; --------------------------------------------------------------------------------------------------
;; Entering Stop mode
;; --------------------------------------------------------------------------------------------------
;; void EnterPWDN(int CLKCON);
;; EnterPWDN() has to be on ROM(0~0x1fffff) for DRAM self-refresh
;; --------------------------------------------------------------------------------------------------
EnterPWDN
mov r10,r0
nop ;Wait until self-refresh is issued. May not be needed.
nop ;If the other bus master holds the bus, ...
nop
nop
nop
nop
nop
;enter POWERDN mode;
ldr r0,=SYSCON
strb r10,[r0]
;wait until enter STOP mode and until wake-up
mov r0,#0xff
0 subs r0,r0,#1
bne %B0
mov pc, lr
LTORG
;; --------------------------------------------------------------------------------------------------
;; System Initialization Setting
;; --------------------------------------------------------------------------------------------------
;; Memory configuration has to be optimized for best performance
;; The following parameter is not optimized.
;; Memory access cycle parameter strategt
;; - Even FP-DRAM, EDO DRAM setting has more late fetch point by half-clock
;; - The memory setting, here, are made the safe parameters even at 25MHz
;; - FP-DRAM parameter :
;; - DRAM refresh rate is for 25MHz
;; --------------------------------------------------------------------------------------------------
SyscfgDataSdram
DCD MEMORY0_SDRAM + SYSCFG_4KB + SFR_STARTADDRESS
ALIGN
SyscfgDataEdoDram
DCD MEMORY0_EDO + SYSCFG_4KB + SFR_STARTADDRESS + CACHE_ON + WRBUF_ON
ALIGN
SMRDATA
DCD (0x8<<21) + (0x0<<10) + TACP_5 + TACC_4 + SM_NO_16_SRAM + PMC_SINGLE + DBW_16
DCD (0x18<<21) + (0x10<<10) + TACP_5 + TACC_3 + SM_16_SRAM + PMC_SINGLE + DBW_16
DCD 0x0 ; Bank2=Disable
DCD 0x0 ; Bank3=Disable
DCD 0x0 ; Bank4=Disable
DCD 0x0 ; Bank5=Disable
[ DRAMTYPE = "SDRAM"
DCD (0x200<<21) + (0x100<<10) + TRP_2 + TRC_2 + CAN_9 + DBW_16
| ;; "DRAM"
DCD (0x200<<21) + (0x100<<10) + TRP_3 + TRC_2 + TCAS_2 + TCP_1 + CAN_10 + DBW_16
]
DCD 0x0 ; Bank7=Disable
DCD (0x4f5<<1) + VSMR_1 + REFRESH_ON + TCH_2 + TCSR_1
ALIGN
AREA RAMData, DATA, READWRITE
^ (_ISR_STARTADDRESS - 0x500)
UserStack # 256
SVCStack # 256
UndefStack # 256
AbortStack # 256
IRQStack # 256
FIQStack # 0
^ _ISR_STARTADDRESS
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;; Don't use the label 'IntVectorTable',
;; because armasm.exe cann't recognize this label correctly.
;; the value is different with an address you think it may be.
IntVectorTable
HandleEINT0 # 4
HandleEINT1 # 4
HandleURX # 4
HandleUTX # 4
HandleUERR # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleTOF0 # 4
HandleTMC0 # 4
HandleTOF1 # 4
HandleTMC1 # 4
HandleTOF2 # 4
HandleTMC2 # 4
HandleTOF3 # 4
HandleTMC3 # 4
HandleTOF4 # 4
HandleTMC4 # 4
HandleBT # 4
HandleSIO0 # 4
HandleSIO1 # 4
HandleIIC # 4
HandleRTCA # 4
HandleRTCT # 4
HandleTF # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4 # 4
HandleADC # 4
HandleEINT8 # 4
HandleEINT9 # 4
HandleEINT10 # 4
HandleEINT11 # 4
HandleUnused # 20
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