#ifndef _ASM_IA64_PAL_H#define _ASM_IA64_PAL_H/* * Processor Abstraction Layer definitions. * * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0 * chapter 11 IA-64 Processor Abstraction Layer * * Copyright (C) 1998-2001 Hewlett-Packard Co *	David Mosberger-Tang <davidm@hpl.hp.com> *	Stephane Eranian <eranian@hpl.hp.com> * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> * * 99/10/01	davidm	Make sure we pass zero for reserved parameters. * 00/03/07	davidm	Updated pal_cache_flush() to be in sync with PAL v2.6. * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added * 00/05/25	eranian Support for stack calls, and static physical calls * 00/06/18	eranian Support for stacked physical calls * 06/10/26	rja	Support for Intel Itanium Architecture Software Developer's *			Manual Rev 2.2 (Jan 2006) *//* * Note that some of these calls use a static-register only calling * convention which has nothing to do with the regular calling * convention. */#define PAL_CACHE_FLUSH		1	/* flush i/d cache */#define PAL_CACHE_INFO		2	/* get detailed i/d cache info */#define PAL_CACHE_INIT		3	/* initialize i/d cache */#define PAL_CACHE_SUMMARY	4	/* get summary of cache hierarchy */#define PAL_MEM_ATTRIB		5	/* list supported memory attributes */#define PAL_PTCE_INFO		6	/* purge TLB info */#define PAL_VM_INFO		7	/* return supported virtual memory features */#define PAL_VM_SUMMARY		8	/* return summary on supported vm features */#define PAL_BUS_GET_FEATURES	9	/* return processor bus interface features settings */#define PAL_BUS_SET_FEATURES	10	/* set processor bus features */#define PAL_DEBUG_INFO		11	/* get number of debug registers */#define PAL_FIXED_ADDR		12	/* get fixed component of processors's directed address */#define PAL_FREQ_BASE		13	/* base frequency of the platform */#define PAL_FREQ_RATIOS		14	/* ratio of processor, bus and ITC frequency */#define PAL_PERF_MON_INFO	15	/* return performance monitor info */#define PAL_PLATFORM_ADDR	16	/* set processor interrupt block and IO port space addr */#define PAL_PROC_GET_FEATURES	17	/* get configurable processor features & settings */#define PAL_PROC_SET_FEATURES	18	/* enable/disable configurable processor features */#define PAL_RSE_INFO		19	/* return rse information */#define PAL_VERSION		20	/* return version of PAL code */#define PAL_MC_CLEAR_LOG	21	/* clear all processor log info */#define PAL_MC_DRAIN		22	/* drain operations which could result in an MCA */#define PAL_MC_EXPECTED		23	/* set/reset expected MCA indicator */#define PAL_MC_DYNAMIC_STATE	24	/* get processor dynamic state */#define PAL_MC_ERROR_INFO	25	/* get processor MCA info and static state */#define PAL_MC_RESUME		26	/* Return to interrupted process */#define PAL_MC_REGISTER_MEM	27	/* Register memory for PAL to use during MCAs and inits */#define PAL_HALT		28	/* enter the low power HALT state */#define PAL_HALT_LIGHT		29	/* enter the low power light halt state*/#define PAL_COPY_INFO		30	/* returns info needed to relocate PAL */#define PAL_CACHE_LINE_INIT	31	/* init tags & data of cache line */#define PAL_PMI_ENTRYPOINT	32	/* register PMI memory entry points with the processor */#define PAL_ENTER_IA_32_ENV	33	/* enter IA-32 system environment */#define PAL_VM_PAGE_SIZE	34	/* return vm TC and page walker page sizes */#define PAL_MEM_FOR_TEST	37	/* get amount of memory needed for late processor test */#define PAL_CACHE_PROT_INFO	38	/* get i/d cache protection info */#define PAL_REGISTER_INFO	39	/* return AR and CR register information*/#define PAL_SHUTDOWN		40	/* enter processor shutdown state */#define PAL_PREFETCH_VISIBILITY	41	/* Make Processor Prefetches Visible */#define PAL_LOGICAL_TO_PHYSICAL 42	/* returns information on logical to physical processor mapping */#define PAL_CACHE_SHARED_INFO	43	/* returns information on caches shared by logical processor */#define PAL_GET_HW_POLICY	48	/* Get current hardware resource sharing policy */#define PAL_SET_HW_POLICY	49	/* Set current hardware resource sharing policy */#define PAL_COPY_PAL		256	/* relocate PAL procedures and PAL PMI */#define PAL_HALT_INFO		257	/* return the low power capabilities of processor */#define PAL_TEST_PROC		258	/* perform late processor self-test */#define PAL_CACHE_READ		259	/* read tag & data of cacheline for diagnostic testing */#define PAL_CACHE_WRITE		260	/* write tag & data of cacheline for diagnostic testing */#define PAL_VM_TR_READ		261	/* read contents of translation register */#define PAL_GET_PSTATE		262	/* get the current P-state */#define PAL_SET_PSTATE		263	/* set the P-state */#define PAL_BRAND_INFO		274	/* Processor branding information */#define PAL_GET_PSTATE_TYPE_LASTSET	0#define PAL_GET_PSTATE_TYPE_AVGANDRESET	1#define PAL_GET_PSTATE_TYPE_AVGNORESET	2#define PAL_GET_PSTATE_TYPE_INSTANT	3#ifndef __ASSEMBLY__#include <linux/types.h>#include <asm/fpu.h>/* * Data types needed to pass information into PAL procedures and * interpret information returned by them. *//* Return status from the PAL procedure */typedef s64				pal_status_t;#define PAL_STATUS_SUCCESS		0	/* No error */#define PAL_STATUS_UNIMPLEMENTED	(-1)	/* Unimplemented procedure */#define PAL_STATUS_EINVAL		(-2)	/* Invalid argument */#define PAL_STATUS_ERROR		(-3)	/* Error */#define PAL_STATUS_CACHE_INIT_FAIL	(-4)	/* Could not initialize the						 * specified level and type of						 * cache without sideeffects						 * and "restrict" was 1						 */#define PAL_STATUS_REQUIRES_MEMORY	(-9)	/* Call requires PAL memory buffer *//* Processor cache level in the hierarchy */typedef u64				pal_cache_level_t;#define PAL_CACHE_LEVEL_L0		0	/* L0 */#define PAL_CACHE_LEVEL_L1		1	/* L1 */#define PAL_CACHE_LEVEL_L2		2	/* L2 *//* Processor cache type at a particular level in the hierarchy */typedef u64				pal_cache_type_t;#define PAL_CACHE_TYPE_INSTRUCTION	1	/* Instruction cache */#define PAL_CACHE_TYPE_DATA		2	/* Data or unified cache */#define PAL_CACHE_TYPE_INSTRUCTION_DATA	3	/* Both Data & Instruction */#ifdef XEN#define PAL_CACHE_TYPE_COHERENT		4	/* Make I&D-cache coherent */#endif#define PAL_CACHE_FLUSH_INVALIDATE	1	/* Invalidate clean lines */#define PAL_CACHE_FLUSH_CHK_INTRS	2	/* check for interrupts/mc while flushing *//* Processor cache line size in bytes  */typedef int				pal_cache_line_size_t;/* Processor cache line state */typedef u64				pal_cache_line_state_t;#define PAL_CACHE_LINE_STATE_INVALID	0	/* Invalid */#define PAL_CACHE_LINE_STATE_SHARED	1	/* Shared */#define PAL_CACHE_LINE_STATE_EXCLUSIVE	2	/* Exclusive */#define PAL_CACHE_LINE_STATE_MODIFIED	3	/* Modified */typedef struct pal_freq_ratio {	u32 den, num;		/* numerator & denominator */} itc_ratio, proc_ratio;typedef	union  pal_cache_config_info_1_s {	struct {		u64		u		: 1,	/* 0 Unified cache ? */				at		: 2,	/* 2-1 Cache mem attr*/				reserved	: 5,	/* 7-3 Reserved */				associativity	: 8,	/* 16-8 Associativity*/				line_size	: 8,	/* 23-17 Line size */				stride		: 8,	/* 31-24 Stride */				store_latency	: 8,	/*39-32 Store latency*/				load_latency	: 8,	/* 47-40 Load latency*/				store_hints	: 8,	/* 55-48 Store hints*/				load_hints	: 8;	/* 63-56 Load hints */	} pcci1_bits;	u64			pcci1_data;} pal_cache_config_info_1_t;typedef	union  pal_cache_config_info_2_s {	struct {		u32		cache_size;		/*cache size in bytes*/		u32		alias_boundary	: 8,	/* 39-32 aliased addr							 * separation for max							 * performance.							 */				tag_ls_bit	: 8,	/* 47-40 LSb of addr*/				tag_ms_bit	: 8,	/* 55-48 MSb of addr*/				reserved	: 8;	/* 63-56 Reserved */	} pcci2_bits;	u64			pcci2_data;} pal_cache_config_info_2_t;typedef struct pal_cache_config_info_s {	pal_status_t			pcci_status;	pal_cache_config_info_1_t	pcci_info_1;	pal_cache_config_info_2_t	pcci_info_2;	u64				pcci_reserved;} pal_cache_config_info_t;#define pcci_ld_hints		pcci_info_1.pcci1_bits.load_hints#define pcci_st_hints		pcci_info_1.pcci1_bits.store_hints#define pcci_ld_latency		pcci_info_1.pcci1_bits.load_latency#define pcci_st_latency		pcci_info_1.pcci1_bits.store_latency#define pcci_stride		pcci_info_1.pcci1_bits.stride#define pcci_line_size		pcci_info_1.pcci1_bits.line_size#define pcci_assoc		pcci_info_1.pcci1_bits.associativity#define pcci_cache_attr		pcci_info_1.pcci1_bits.at#define pcci_unified		pcci_info_1.pcci1_bits.u#define pcci_tag_msb		pcci_info_2.pcci2_bits.tag_ms_bit#define pcci_tag_lsb		pcci_info_2.pcci2_bits.tag_ls_bit#define pcci_alias_boundary	pcci_info_2.pcci2_bits.alias_boundary#define pcci_cache_size		pcci_info_2.pcci2_bits.cache_size/* Possible values for cache attributes */#define PAL_CACHE_ATTR_WT		0	/* Write through cache */#define PAL_CACHE_ATTR_WB		1	/* Write back cache */#define PAL_CACHE_ATTR_WT_OR_WB		2	/* Either write thru or write						 * back depending on TLB						 * memory attributes						 *//* Possible values for cache hints */#define PAL_CACHE_HINT_TEMP_1		0	/* Temporal level 1 */#define PAL_CACHE_HINT_NTEMP_1		1	/* Non-temporal level 1 */#define PAL_CACHE_HINT_NTEMP_ALL	3	/* Non-temporal all levels *//* Processor cache protection  information */typedef union pal_cache_protection_element_u {	u32			pcpi_data;	struct {		u32		data_bits	: 8, /* # data bits covered by						      * each unit of protection						      */				tagprot_lsb	: 6, /* Least -do- */				tagprot_msb	: 6, /* Most Sig. tag address						      * bit that this						      * protection covers.						      */				prot_bits	: 6, /* # of protection bits */				method		: 4, /* Protection method */				t_d		: 2; /* Indicates which part						      * of the cache this						      * protection encoding						      * applies.						      */	} pcp_info;} pal_cache_protection_element_t;#define pcpi_cache_prot_part	pcp_info.t_d#define pcpi_prot_method	pcp_info.method#define pcpi_prot_bits		pcp_info.prot_bits#define pcpi_tagprot_msb	pcp_info.tagprot_msb#define pcpi_tagprot_lsb	pcp_info.tagprot_lsb#define pcpi_data_bits		pcp_info.data_bits/* Processor cache part encodings */#define PAL_CACHE_PROT_PART_DATA	0	/* Data protection  */#define PAL_CACHE_PROT_PART_TAG		1	/* Tag  protection */#define PAL_CACHE_PROT_PART_TAG_DATA	2	/* Tag+data protection (tag is						 * more significant )						 */#define PAL_CACHE_PROT_PART_DATA_TAG	3	/* Data+tag protection (data is						 * more significant )						 */#define PAL_CACHE_PROT_PART_MAX		6typedef struct pal_cache_protection_info_s {	pal_status_t			pcpi_status;	pal_cache_protection_element_t	pcp_info[PAL_CACHE_PROT_PART_MAX];} pal_cache_protection_info_t;/* Processor cache protection method encodings */#define PAL_CACHE_PROT_METHOD_NONE		0	/* No protection */#define PAL_CACHE_PROT_METHOD_ODD_PARITY	1	/* Odd parity */#define PAL_CACHE_PROT_METHOD_EVEN_PARITY	2	/* Even parity */#define PAL_CACHE_PROT_METHOD_ECC		3	/* ECC protection *//* Processor cache line identification in the hierarchy */typedef union pal_cache_line_id_u {	u64			pclid_data;	struct {		u64		cache_type	: 8,	/* 7-0 cache type */				level		: 8,	/* 15-8 level of the							 * cache in the							 * hierarchy.							 */				way		: 8,	/* 23-16 way in the set							 */				part		: 8,	/* 31-24 part of the							 * cache							 */				reserved	: 32;	/* 63-32 is reserved*/	} pclid_info_read;	struct {		u64		cache_type	: 8,	/* 7-0 cache type */				level		: 8,	/* 15-8 level of the							 * cache in the							 * hierarchy.							 */				way		: 8,	/* 23-16 way in the set							 */				part		: 8,	/* 31-24 part of the							 * cache							 */				mesi		: 8,	/* 39-32 cache line							 * state							 */				start		: 8,	/* 47-40 lsb of data to							 * invert							 */				length		: 8,	/* 55-48 #bits to							 * invert							 */				trigger		: 8;	/* 63-56 Trigger error							 * by doing a load							 * after the write							 */	} pclid_info_write;} pal_cache_line_id_u_t;#define pclid_read_part		pclid_info_read.part#define pclid_read_way		pclid_info_read.way#define pclid_read_level	pclid_info_read.level#define pclid_read_cache_type	pclid_info_read.cache_type#define pclid_write_trigger	pclid_info_write.trigger#define pclid_write_length	pclid_info_write.length#define pclid_write_start	pclid_info_write.start#define pclid_write_mesi	pclid_info_write.mesi#define pclid_write_part	pclid_info_write.part#define pclid_write_way		pclid_info_write.way#define pclid_write_level	pclid_info_write.level#define pclid_write_cache_type	pclid_info_write.cache_type/* Processor cache line part encodings */#define PAL_CACHE_LINE_ID_PART_DATA		0	/* Data */#define PAL_CACHE_LINE_ID_PART_TAG		1	/* Tag */#define PAL_CACHE_LINE_ID_PART_DATA_PROT	2	/* Data protection */#define PAL_CACHE_LINE_ID_PART_TAG_PROT		3	/* Tag protection */#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT	4	/* Data+tag							 * protection							 */typedef struct pal_cache_line_info_s {	pal_status_t		pcli_status;		/* Return status of the read cache line							 * info call.							 */	u64			pcli_data;		/* 64-bit data, tag, protection bits .. */	u64			pcli_data_len;		/* data length in bits */	pal_cache_line_state_t	pcli_cache_line_state;	/* mesi state */} pal_cache_line_info_t;/* Machine Check related crap *//* Pending event status bits  */typedef u64					pal_mc_pending_events_t;#define PAL_MC_PENDING_MCA			(1 << 0)#define PAL_MC_PENDING_INIT			(1 << 1)/* Error information type */typedef u64					pal_mc_info_index_t;#define PAL_MC_INFO_PROCESSOR			0	/* Processor */#define PAL_MC_INFO_CACHE_CHECK			1	/* Cache check */#define PAL_MC_INFO_TLB_CHECK			2	/* Tlb check */#define PAL_MC_INFO_BUS_CHECK			3	/* Bus check */#define PAL_MC_INFO_REQ_ADDR			4	/* Requestor address */#define PAL_MC_INFO_RESP_ADDR			5	/* Responder address */#define PAL_MC_INFO_TARGET_ADDR			6	/* Target address */#define PAL_MC_INFO_IMPL_DEP			7	/* Implementation							 * dependent							 */#define PAL_TLB_CHECK_OP_PURGE			8typedef struct pal_process_state_info_s {	u64		reserved1	: 2,			rz		: 1,	/* PAL_CHECK processor						 * rendezvous						 * successful.						 */			ra		: 1,	/* PAL_CHECK attempted						 * a rendezvous.						 */			me		: 1,	/* Distinct multiple						 * errors occurred						 */			mn		: 1,	/* Min. state save						 * area has been						 * registered with PAL						 */			sy		: 1,	/* Storage integrity						 * synched						 */			co		: 1,	/* Continuable */			ci		: 1,	/* MC isolated */			us		: 1,	/* Uncontained storage						 * damage.						 */			hd		: 1,	/* Non-essential hw						 * lost (no loss of						 * functionality)						 * causing the						 * processor to run in						 * degraded mode.						 */			tl		: 1,	/* 1 => MC occurred						 * after an instr was						 * executed but before						 * the trap that						 * resulted from instr						 * execution was						 * generated.						 * (Trap Lost )						 */			mi		: 1,	/* More information available						 * call PAL_MC_ERROR_INFO						 */			pi		: 1,	/* Precise instruction pointer */			pm		: 1,	/* Precise min-state save area */			dy		: 1,	/* Processor dynamic						 * state valid						 */