} pal_perf_mon_info_u_t;/* Return the performance monitor information about what can be counted * and how to configure the monitors to count the desired events. */static inline s64ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);	if (pm_info)		pm_info->ppmi_data = iprv.v0;	return iprv.status;}/* Specifies the physical address of the processor interrupt block * and I/O port space. */static inline s64ia64_pal_platform_addr (u64 type, u64 physical_addr){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);	return iprv.status;}/* Set the SAL PMI entrypoint in memory */static inline s64ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);	return iprv.status;}struct pal_features_s;/* Provide information about configurable processor features */static inline s64ia64_pal_proc_get_features (u64 *features_avail,			    u64 *features_status,			    u64 *features_control){	struct ia64_pal_retval iprv;	PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);	if (iprv.status == 0) {		*features_avail   = iprv.v0;		*features_status  = iprv.v1;		*features_control = iprv.v2;	}	return iprv.status;}/* Enable/disable processor dependent features */static inline s64ia64_pal_proc_set_features (u64 feature_select){	struct ia64_pal_retval iprv;	PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);	return iprv.status;}/* * Put everything in a struct so we avoid the global offset table whenever * possible. */typedef struct ia64_ptce_info_s {	u64		base;	u32		count[2];	u32		stride[2];} ia64_ptce_info_t;/* Return the information required for the architected loop used to purge * (initialize) the entire TC */static inline s64ia64_get_ptce (ia64_ptce_info_t *ptce){	struct ia64_pal_retval iprv;	if (!ptce)		return -1;	PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);	if (iprv.status == 0) {		ptce->base = iprv.v0;		ptce->count[0] = iprv.v1 >> 32;		ptce->count[1] = iprv.v1 & 0xffffffff;		ptce->stride[0] = iprv.v2 >> 32;		ptce->stride[1] = iprv.v2 & 0xffffffff;	}	return iprv.status;}/* Return info about implemented application and control registers. */static inline s64ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);	if (reg_info_1)		*reg_info_1 = iprv.v0;	if (reg_info_2)		*reg_info_2 = iprv.v1;	return iprv.status;}typedef union pal_hints_u {	u64			ph_data;	struct {	       u64		si		: 1,				li		: 1,				reserved	: 62;	} pal_hints_s;} pal_hints_u_t;/* Return information about the register stack and RSE for this processor * implementation. */static inline s64ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);	if (num_phys_stacked)		*num_phys_stacked = iprv.v0;	if (hints)		hints->ph_data = iprv.v1;	return iprv.status;}/* * Set the current hardware resource sharing policy of the processor */static inline s64ia64_pal_set_hw_policy (u64 policy){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);	return iprv.status;}/* Cause the processor to enter	SHUTDOWN state, where prefetching and execution are * suspended, but cause cache and TLB coherency to be maintained. * This is usually called in IA-32 mode. */static inline s64ia64_pal_shutdown (void){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);	return iprv.status;}/* Perform the second phase of processor self-test. */static inline s64ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);	if (self_test_state)		*self_test_state = iprv.v0;	return iprv.status;}typedef union  pal_version_u {	u64	pal_version_val;	struct {		u64	pv_pal_b_rev		:	8;		u64	pv_pal_b_model		:	8;		u64	pv_reserved1		:	8;		u64	pv_pal_vendor		:	8;		u64	pv_pal_a_rev		:	8;		u64	pv_pal_a_model		:	8;		u64	pv_reserved2		:	16;	} pal_version_s;} pal_version_u_t;/* * Return PAL version information.  While the documentation states that * PAL_VERSION can be called in either physical or virtual mode, some * implementations only allow physical calls.  We don't call it very often, * so the overhead isn't worth eliminating. */static inline s64ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version){	struct ia64_pal_retval iprv;	PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);	if (pal_min_version)		pal_min_version->pal_version_val = iprv.v0;	if (pal_cur_version)		pal_cur_version->pal_version_val = iprv.v1;	return iprv.status;}typedef union pal_tc_info_u {	u64			pti_val;	struct {	       u64		num_sets	:	8,				associativity	:	8,				num_entries	:	16,				pf		:	1,				unified		:	1,				reduce_tr	:	1,				reserved	:	29;	} pal_tc_info_s;} pal_tc_info_u_t;#define tc_reduce_tr		pal_tc_info_s.reduce_tr#define tc_unified		pal_tc_info_s.unified#define tc_pf			pal_tc_info_s.pf#define tc_num_entries		pal_tc_info_s.num_entries#define tc_associativity	pal_tc_info_s.associativity#define tc_num_sets		pal_tc_info_s.num_sets/* Return information about the virtual memory characteristics of the processor * implementation. */static inline s64ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);	if (tc_info)		tc_info->pti_val = iprv.v0;	if (tc_pages)		*tc_pages = iprv.v1;	return iprv.status;}/* Get page size information about the virtual memory characteristics of the processor * implementation. */static inline s64ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);	if (tr_pages)		*tr_pages = iprv.v0;	if (vw_pages)		*vw_pages = iprv.v1;	return iprv.status;}typedef union pal_vm_info_1_u {	u64			pvi1_val;	struct {		u64		vw		: 1,				phys_add_size	: 7,				key_size	: 8,				max_pkr		: 8,				hash_tag_id	: 8,				max_dtr_entry	: 8,				max_itr_entry	: 8,				max_unique_tcs	: 8,				num_tc_levels	: 8;	} pal_vm_info_1_s;} pal_vm_info_1_u_t;#define PAL_MAX_PURGES		0xFFFF		/* all ones is means unlimited */typedef union pal_vm_info_2_u {	u64			pvi2_val;	struct {		u64		impl_va_msb	: 8,				rid_size	: 8,				max_purges	: 16,				reserved	: 32;	} pal_vm_info_2_s;} pal_vm_info_2_u_t;/* Get summary information about the virtual memory characteristics of the processor * implementation. */static inline s64ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);	if (vm_info_1)		vm_info_1->pvi1_val = iprv.v0;	if (vm_info_2)		vm_info_2->pvi2_val = iprv.v1;	return iprv.status;}typedef union pal_itr_valid_u {	u64			piv_val;	struct {	       u64		access_rights_valid	: 1,				priv_level_valid	: 1,				dirty_bit_valid		: 1,				mem_attr_valid		: 1,				reserved		: 60;	} pal_tr_valid_s;} pal_tr_valid_u_t;/* Read a translation register */static inline s64ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid){	struct ia64_pal_retval iprv;	PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));	if (tr_valid)		tr_valid->piv_val = iprv.v0;	return iprv.status;}/* * PAL_PREFETCH_VISIBILITY transaction types */#define PAL_VISIBILITY_VIRTUAL		0#define PAL_VISIBILITY_PHYSICAL		1/* * PAL_PREFETCH_VISIBILITY return codes */#define PAL_VISIBILITY_OK		1#define PAL_VISIBILITY_OK_REMOTE_NEEDED	0#define PAL_VISIBILITY_INVAL_ARG	-2#define PAL_VISIBILITY_ERROR		-3static inline s64ia64_pal_prefetch_visibility (s64 trans_type){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);	return iprv.status;}/* data structure for getting information on logical to physical mappings */typedef union pal_log_overview_u {	struct {		u64	num_log		:16,	/* Total number of logical						 * processors on this die						 */			tpc		:8,	/* Threads per core */			reserved3	:8,	/* Reserved */			cpp		:8,	/* Cores per processor */			reserved2	:8,	/* Reserved */			ppid		:8,	/* Physical processor ID */			reserved1	:8;	/* Reserved */	} overview_bits;	u64 overview_data;} pal_log_overview_t;typedef union pal_proc_n_log_info1_u{	struct {		u64	tid		:16,	/* Thread id */			reserved2	:16,	/* Reserved */			cid		:16,	/* Core id */			reserved1	:16;	/* Reserved */	} ppli1_bits;	u64	ppli1_data;} pal_proc_n_log_info1_t;typedef union pal_proc_n_log_info2_u {	struct {		u64	la		:16,	/* Logical address */			reserved	:48;	/* Reserved */	} ppli2_bits;	u64	ppli2_data;} pal_proc_n_log_info2_t;typedef struct pal_logical_to_physical_s{	pal_log_overview_t overview;	pal_proc_n_log_info1_t ppli1;	pal_proc_n_log_info2_t ppli2;} pal_logical_to_physical_t;#define overview_num_log	overview.overview_bits.num_log#define overview_tpc		overview.overview_bits.tpc#define overview_cpp		overview.overview_bits.cpp#define overview_ppid		overview.overview_bits.ppid#define log1_tid		ppli1.ppli1_bits.tid#define log1_cid		ppli1.ppli1_bits.cid#define log2_la			ppli2.ppli2_bits.la/* Get information on logical to physical processor mappings. */static inline s64ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);	if (iprv.status == PAL_STATUS_SUCCESS)	{		mapping->overview.overview_data = iprv.v0;		mapping->ppli1.ppli1_data = iprv.v1;		mapping->ppli2.ppli2_data = iprv.v2;	}	return iprv.status;}typedef struct pal_cache_shared_info_s{	u64 num_shared;	pal_proc_n_log_info1_t ppli1;	pal_proc_n_log_info2_t ppli2;} pal_cache_shared_info_t;/* Get information on logical to physical processor mappings. */static inline s64ia64_pal_cache_shared_info(u64 level,		u64 type,		u64 proc_number,		pal_cache_shared_info_t *info){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);	if (iprv.status == PAL_STATUS_SUCCESS) {		info->num_shared = iprv.v0;		info->ppli1.ppli1_data = iprv.v1;		info->ppli2.ppli2_data = iprv.v2;	}	return iprv.status;}#ifdef XEN#include <asm/vmx_pal.h>#endif#endif /* __ASSEMBLY__ */#endif /* _ASM_IA64_PAL_H */