?? iocc2430.h
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/**************************************************************************************************
* - ioCC2430.h -
*
* Special header for the Chipcon CC2430 System on Chip.
*
**************************************************************************************************
*/
#ifndef IOCC2430_H
#define IOCC2430_H
/* ------------------------------------------------------------------------------------------------
* Compiler Abstraction
* ------------------------------------------------------------------------------------------------
*/
#ifdef __IAR_SYSTEMS_ICC__
#pragma language=extended
#define SFR(name,addr) __sfr __no_init volatile unsigned char name @ addr;
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) \
__sfr __no_init volatile union \
{ \
unsigned char name; \
struct { \
unsigned char bit0 : 1; \
unsigned char bit1 : 1; \
unsigned char bit2 : 1; \
unsigned char bit3 : 1; \
unsigned char bit4 : 1; \
unsigned char bit5 : 1; \
unsigned char bit6 : 1; \
unsigned char bit7 : 1; \
}; \
} @ addr;
#define SBIT(name,addr) /* not in use for IAR C Compiler */
#define XREG(addr) ((unsigned char volatile __xdata *) 0)[addr]
#define VECT(num,addr) addr
#elif defined __IAR_SYSTEMS_ASM__
#define SFR(name,addr) name DEFINE addr
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) name DEFINE addr
#define SBIT(name,addr) name DEFINE addr
#define XREG(addr) addr
#define VECT(num,addr) addr
/* IAR assembler uses some predefined registers. The following prevents name collisions. */
#define SP SPx
#define ACC ACCx
#define B Bx
#define PSW PSWx
#define CY CYx
#define AC ACx
#define F0 F0x
#define RS1 RS1x
#define RS0 RS0x
#define OV OVx
#define P Px
#elif defined __KEIL__
#define SFR(name,addr) sfr name = addr;
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) sfr name = addr;
#define SBIT(name,addr) sbit name = addr;
#define VECT(num,addr) num
#ifdef __C51__
#define XREG(addr) ((unsigned char volatile xdata *) 0)[addr]
#elif defined __AX51__ || defined __A51__
#define XREG(addr) addr
#else
#error "Unknown Keil compiler."
#endif
#else
#error "Unrecognized compiler."
#endif
/* ------------------------------------------------------------------------------------------------
* Interrupt Vectors
* ------------------------------------------------------------------------------------------------
*/
#define RFERR_VECTOR VECT( 0, 0x03 ) /* RF TX FIFO Underflow and RX FIFO Overflow */
#define ADC_VECTOR VECT( 1, 0x0B ) /* ADC End of Conversion */
#define URX0_VECTOR VECT( 2, 0x13 ) /* USART0 RX Complete */
#define URX1_VECTOR VECT( 3, 0x1B ) /* USART1 RX Complete */
#define ENC_VECTOR VECT( 4, 0x23 ) /* AES Encryption/Decryption Complete */
#define ST_VECTOR VECT( 5, 0x2B ) /* Sleep Timer Compare */
#define P2INT_VECTOR VECT( 6, 0x33 ) /* Port 2 Inputs */
#define UTX0_VECTOR VECT( 7, 0x3B ) /* USART0 TX Complete */
#define DMA_VECTOR VECT( 8, 0x43 ) /* DMA Transfer Complete */
#define T1_VECTOR VECT( 9, 0x4B ) /* Timer 1 (16-bit) Capture/Compare/Overflow */
#define T2_VECTOR VECT( 10, 0x53 ) /* Timer 2 (MAC Timer) */
#define T3_VECTOR VECT( 11, 0x5B ) /* Timer 3 (8-bit) Capture/Compare/Overflow */
#define T4_VECTOR VECT( 12, 0x63 ) /* Timer 4 (8-bit) Capture/Compare/Overflow */
#define P0INT_VECTOR VECT( 13, 0x6B ) /* Port 0 Inputs */
#define UTX1_VECTOR VECT( 14, 0x73 ) /* USART1 TX Complete */
#define P1INT_VECTOR VECT( 15, 0x7B ) /* Port 1 Inputs */
#define RF_VECTOR VECT( 16, 0x83 ) /* RF General Interrupts */
#define WDT_VECTOR VECT( 17, 0x8B ) /* Watchdog Overflow in Timer Mode */
/* ------------------------------------------------------------------------------------------------
* SFRs
* ------------------------------------------------------------------------------------------------
*/
/* Port 0 */
SFRBIT( P0 , 0x80, P0_7, P0_6, P0_5, P0_4, P0_3, P0_2, P0_1, P0_0 )
SFR( SP , 0x81 ) /* Stack Pointer */
SFR( DPL0 , 0x82 ) /* Data Pointer 0 Low Byte */
SFR( DPH0 , 0x83 ) /* Data Pointer 0 High Byte */
SFR( DPL1 , 0x84 ) /* Data Pointer 1 Low Byte */
SFR( DPH1 , 0x85 ) /* Data Pointer 1 High Byte */
SFR( U0CSR , 0x86 ) /* USART 0 Control and Status */
SFR( PCON , 0x87 ) /* Power Mode Control */
/* Interrupt Flags */
SFRBIT( TCON , 0x88, URX1IF, _TCON6, ADCIF, _TCON5, URX0IF, IT1, RFERRIF, IT0 )
SFR( P0IFG , 0x89 ) /* Port 0 Interrupt Status Flag */
SFR( P1IFG , 0x8A ) /* Port 1 Interrupt Status Flag */
SFR( P2IFG , 0x8B ) /* Port 2 Interrupt Status Flag */
SFR( PICTL , 0x8C ) /* Port Interrupt Control */
SFR( P1IEN , 0x8D ) /* Port 1 Interrupt Mask */
SFR( _SFR8E , 0x8E ) /* not used */
SFR( P0INP , 0x8F ) /* Port 0 Input Mode */
/* Port 1 */
SFRBIT( P1 , 0x90, P1_7, P1_6, P1_5, P1_4, P1_3, P1_2, P1_1, P1_0 )
SFR( RFIM , 0x91 ) /* RF Interrupt Mask */
SFR( DPS , 0x92 ) /* Data Pointer Select */
SFR( MPAGE , 0x93 ) /* Memory Page Select */
SFR( T2CMP , 0x94 ) /* Timer 2 Compare Value */
SFR( ST0 , 0x95 ) /* Sleep Timer 0 */
SFR( ST1 , 0x96 ) /* Sleep Timer 1 */
SFR( ST2 , 0x97 ) /* Sleep Timer 2 */
/* Interrupt Flags 2 */
SFRBIT( S0CON , 0x98, _SOCON7, _SOCON6, _SOCON5, _SOCON4, _SOCON3, _SOCON2, ENCIF_1, ENCIF_0 )
SFR( _SFR99 , 0x99 ) /* not used */
SFR( IEN2 , 0x9A ) /* Interrupt Enable 2 */
SFR( S1CON , 0x9B ) /* Interrupt Flags 3 */
SFR( T2PEROF0 , 0x9C ) /* Timer 2 Overflow Count 0 */
SFR( T2PEROF1 , 0x9D ) /* Timer 2 Overflow Count 1 */
SFR( T2PEROF2 , 0x9E ) /* Timer 2 Overflow Count 2 */
SFR( _SFR9F , 0x9F ) /* not used */
/* Port 2 */
SFRBIT( P2 , 0xA0, _P2_7, _P2_6, _P2_5, P2_4, P2_3, P2_2, P2_1, P2_0 )
SFR( T2OF0 , 0xA1 ) /* Timer 2 Overflow Count 0 */
SFR( T2OF1 , 0xA2 ) /* Timer 2 Overflow Count 1 */
SFR( T2OF2 , 0xA3 ) /* Timer 2 Overflow Count 2 */
SFR( T2CAPLPL , 0xA4 ) /* Timer 2 Period Low Byte */
SFR( T2CAPHPH , 0xA5 ) /* Timer 2 Period High Byte */
SFR( T2TLD , 0xA6 ) /* Timer 2 Timer Value Low Byte */
SFR( T2THD , 0xA7 ) /* Timer 2 Timer Value High Byte */
/* Interrupt Enable 0 */
SFRBIT( IEN0 , 0xA8, EA, _IEN06, STIE, ENCIE, URX1IE, URX0IE, ADCIE, RFERRIE )
SFR( IP0 , 0xA9 ) /* Interrupt Priority 0 */
SFR( _SFRAA , 0xAA ) /* not used */
SFR( FWT , 0xAB ) /* Flash Write Timing */
SFR( FADDRL , 0xAC ) /* Flash Address Low Byte */
SFR( FADDRH , 0xAD ) /* Flash Address High Byte */
SFR( FCTL , 0xAE ) /* Flash Control */
SFR( FWDATA , 0xAF ) /* Flash Write Data */
SFR( _SFRB0 , 0xB0 ) /* not used */
SFR( ENCDI , 0xB1 ) /* Encryption Input Data */
SFR( ENCDO , 0xB2 ) /* Encryption Output Data */
SFR( ENCCS , 0xB3 ) /* Encryption Control and Status */
SFR( ADCCON1 , 0xB4 ) /* ADC Control 1 */
SFR( ADCCON2 , 0xB5 ) /* ADC Control 2 */
SFR( ADCCON3 , 0xB6 ) /* ADC Control 3 */
SFR( _SFRB7 , 0xB7 ) /* not used */
/* Interrupt Enable 1 */
SFRBIT( IEN1 , 0xB8, _IEN17, _IEN16, P0IE, T4IE, T3IE, T2IE, T1IE, DMAIE )
SFR( IP1 , 0xB9 ) /* Interrupt Priority 1 */
SFR( ADCL , 0xBA ) /* ADC Data Low */
SFR( ADCH , 0xBB ) /* ADC Data High */
SFR( RNDL , 0xBC ) /* Random Register Low Byte */
SFR( RNDH , 0xBD ) /* Random Register High Byte */
SFR( SLEEP , 0xBE ) /* Sleep Mode Control */
SFR( _SFRBF , 0xBF ) /* not used */
/* Interrupt Flags 4 */
SFRBIT( IRCON , 0xC0 ,STIF, _IRCON6, P0IF, T4IF, T3IF, T2IF, T1IF, DMAIF )
SFR( U0DBUF , 0xC1 ) /* USART 0 Receive/Transmit Data Buffer */
SFR( U0BAUD , 0xC2 ) /* USART 0 Baud Rate Control */
SFR( T2CNF , 0xC3 ) /* Timer 2 Configuration */
SFR( U0UCR , 0xC4 ) /* USART 0 UART Control */
SFR( U0GCR , 0xC5 ) /* USART 0 Generic Control */
SFR( CLKCON , 0xC6 ) /* Clock Control */
SFR( MEMCTR , 0xC7 ) /* Memory Arbiter Control */
SFR( T2CON , 0xC8 ) /* Interrupt Control */
SFR( WDCTL , 0xC9 ) /* Watchdog Timer Control */
SFR( T3CNT , 0xCA ) /* Timer 3 Counter */
SFR( T3CTL , 0xCB ) /* Timer 3 Control */
SFR( T3CCTL0 , 0xCC ) /* Timer 3 Channel 0 Capture/Compare Control */
SFR( T3CC0 , 0xCD ) /* Timer 3 Channel 0 Capture/Compare Value */
SFR( T3CCTL1 , 0xCE ) /* Timer 3 Channel 1 Capture/Compare Control */
SFR( T3CC1 , 0xCF ) /* Timer 3 Channel 1 Capture/Compare Value */
/* Program Status Word */
SFRBIT( PSW , 0xD0, CY, AC, F0, RS1, RS0, OV, F1, P)
SFR( DMAIRQ , 0xD1 ) /* DMA Interrupt Flag */
SFR( DMA1CFGL , 0xD2 ) /* DMA Channel 1-4 Configuration Address Low Byte */
SFR( DMA1CFGH , 0xD3 ) /* DMA Channel 1-4 Configuration Address High Byte */
SFR( DMA0CFGL , 0xD4 ) /* DMA Channel 0 Configuration Address Low Byte */
SFR( DMA0CFGH , 0xD5 ) /* DMA Channel 0 Configuration Address High Byte */
SFR( DMAARM , 0xD6 ) /* DMA Channel Arm */
SFR( DMAREQ , 0xD7 ) /* DMA Channel Start Request and Status */
/* Timers 1/3/4 Interrupt Mask/Flag */
SFRBIT( TIMIF , 0xD8 , _TIMIF7, OVFIM, T4CH1IF, T4CH0IF, T4OVFIF, T3CH1IF, T3CH0IF, T3OVFIF )
SFR( RFD , 0xD9 ) /* RF Data */
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