?? iocc2430.h
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SFR( T1CC0L , 0xDA ) /* Timer 1 Channel 0 Capture/Compare Value Low Byte */
SFR( T1CC0H , 0xDB ) /* Timer 1 Channel 0 Capture/Compare Value High Byte */
SFR( T1CC1L , 0xDC ) /* Timer 1 Channel 1 Capture/Compare Value Low Byte */
SFR( T1CC1H , 0xDD ) /* Timer 1 Channel 1 Capture/Compare Value High Byte */
SFR( T1CC2L , 0xDE ) /* Timer 1 Channel 2 Capture/Compare Value Low Byte */
SFR( T1CC2H , 0xDF ) /* Timer 1 Channel 2 Capture/Compare Value High Byte */
SFR( ACC , 0xE0 ) /* Accumulator */
SFR( RFST , 0xE1 ) /* RF CSMA-CA / Strobe Processor */
SFR( T1CNTL , 0xE2 ) /* Timer 1 Counter Low */
SFR( T1CNTH , 0xE3 ) /* Timer 1 Counter High */
SFR( T1CTL , 0xE4 ) /* Timer 1 Control and Status */
SFR( T1CCTL0 , 0xE5 ) /* Timer 1 Channel 0 Capture/Compare Control */
SFR( T1CCTL1 , 0xE6 ) /* Timer 1 Channel 1 Capture/Compare Control */
SFR( T1CCTL2 , 0xE7 ) /* Timer 1 Channel 2 Capture/Compare Control */
/* Interrupt Flags 5 */
SFRBIT( IRCON2 , 0xE8,_IRCON27, _IRCON26, _IRCON25, WDTIF, P1IF, UTX1IF, UTX0IF, P2IF )
SFR( RFIF , 0xE9 ) /* RF Interrupt Flags */
SFR( T4CNT , 0xEA ) /* Timer 4 Counter */
SFR( T4CTL , 0xEB ) /* Timer 4 Control */
SFR( T4CCTL0 , 0xEC ) /* Timer 4 Channel 0 Capture/Compare Control */
SFR( T4CC0 , 0xED ) /* Timer 4 Channel 0 Capture/Compare Value */
SFR( T4CCTL1 , 0xEE ) /* Timer 4 Channel 1 Capture/Compare Control */
SFR( T4CC1 , 0xEF ) /* Timer 4 Channel 1 Capture/Compare Value */
SFR( B , 0xF0 ) /* B Register */
SFR( PERCFG , 0xF1 ) /* Peripheral Control */
SFR( ADCCFG , 0xF2 ) /* ADC Input Configuration */
SFR( P0SEL , 0xF3 ) /* Port 0 Function Select */
SFR( P1SEL , 0xF4 ) /* Port 1 Function Select */
SFR( P2SEL , 0xF5 ) /* Port 2 Function Select */
SFR( P1INP , 0xF6 ) /* Port 1 Input Mode */
SFR( P2INP , 0xF7 ) /* Port 2 Input Mode */
SFR( U1CSR , 0xF8 ) /* USART 1 Control and Status */
SFR( U1DBUF , 0xF9 ) /* USART 1 Receive/Transmit Data Buffer */
SFR( U1BAUD , 0xFA ) /* USART 1 Baud Rate Control */
SFR( U1UCR , 0xFB ) /* USART 1 UART Control */
SFR( U1GCR , 0xFC ) /* USART 1 Generic Control */
SFR( P0DIR , 0xFD ) /* Port 0 Direction */
SFR( P1DIR , 0xFE ) /* Port 1 Direction */
SFR( P2DIR , 0xFF ) /* Port 2 Direction */
/* ------------------------------------------------------------------------------------------------
* SFR Bit Access
* ------------------------------------------------------------------------------------------------
*/
/* P0 */
SBIT( P0_7 , 0x87 ) /* GPIO - Port 0, Input 7 */
SBIT( P0_6 , 0x86 ) /* GPIO - Port 0, Input 6 */
SBIT( P0_5 , 0x85 ) /* GPIO - Port 0, Input 5 */
SBIT( P0_4 , 0x84 ) /* GPIO - Port 0, Input 4 */
SBIT( P0_3 , 0x83 ) /* GPIO - Port 0, Input 3 */
SBIT( P0_2 , 0x82 ) /* GPIO - Port 0, Input 2 */
SBIT( P0_1 , 0x81 ) /* GPIO - Port 0, Input 1 */
SBIT( P0_0 , 0x80 ) /* GPIO - Port 0, Input 0 */
/* TCON */
SBIT( URX1IF , 0x8F ) /* USART1 RX Interrupt Flag */
SBIT( _TCON6 , 0x8E ) /* not used */
SBIT( ADCIF , 0x8D ) /* ADC Interrupt Flag */
SBIT( _TCON5 , 0x8C ) /* not used */
SBIT( URX0IF , 0x8B ) /* USART0 RX Interrupt Flag */
SBIT( IT1 , 0x8A ) /* reserved (must always be set to 1) */
SBIT( RFERRIF , 0x89 ) /* RF TX/RX FIFO Interrupt Flag */
SBIT( IT0 , 0x88 ) /* reserved (must always be set to 1) */
/* P1 */
SBIT( P1_7 , 0x97 ) /* GPIO - Port 1, Input 7 */
SBIT( P1_6 , 0x96 ) /* GPIO - Port 1, Input 6 */
SBIT( P1_5 , 0x95 ) /* GPIO - Port 1, Input 5 */
SBIT( P1_4 , 0x94 ) /* GPIO - Port 1, Input 4 */
SBIT( P1_3 , 0x93 ) /* GPIO - Port 1, Input 3 */
SBIT( P1_2 , 0x92 ) /* GPIO - Port 1, Input 2 */
SBIT( P1_1 , 0x91 ) /* GPIO - Port 1, Input 1 */
SBIT( P1_0 , 0x90 ) /* GPIO - Port 1, Input 0 */
/* S0CON */
SBIT( ENCIF_1 , 0x99 ) /* AES Interrupt Flag 1 */
SBIT( ENCIF_0 , 0x98 ) /* AES Interrupt Flag 0 */
/* P2 */
SBIT( _P2_7 , 0xA7 ) /* not used */
SBIT( _P2_6 , 0xA6 ) /* not used */
SBIT( _P2_5 , 0xA5 ) /* not used */
SBIT( P2_4 , 0xA4 ) /* GPIO - Port 2, Input 4 */
SBIT( P2_3 , 0xA3 ) /* GPIO - Port 2, Input 3 */
SBIT( P2_2 , 0xA2 ) /* GPIO - Port 2, Input 2 */
SBIT( P2_1 , 0xA1 ) /* GPIO - Port 2, Input 1 */
SBIT( P2_0 , 0xA0 ) /* GPIO - Port 2, Input 0 */
/* IEN0 */
SBIT( EA , 0xAF ) /* Global Interrupt Enable */
SBIT( _IEN06 , 0xAE ) /* not used */
SBIT( STIE , 0xAD ) /* Sleep Timer Interrupt Enable */
SBIT( ENCIE , 0xAC ) /* AES Encryption/Decryption Interrupt Enable */
SBIT( URX1IE , 0xAB ) /* USART1 RX Interrupt Enable */
SBIT( URX0IE , 0xAA ) /* USART0 RX Interrupt Enable */
SBIT( ADCIE , 0xA9 ) /* ADC Interrupt Enable */
SBIT( RFERRIE , 0xA8 ) /* RF TX/RX FIFO Interrupt Enable */
/* IEN1 */
SBIT( _IEN17 , 0xBF ) /* not used */
SBIT( _IEN16 , 0xBE ) /* not used */
SBIT( P0IE , 0xBD ) /* Port 0 Interrupt Enable */
SBIT( T4IE , 0xBC ) /* Timer 4 Interrupt Enable */
SBIT( T3IE , 0xBB ) /* Timer 3 Interrupt Enable */
SBIT( T2IE , 0xBA ) /* Timer 2 Interrupt Enable */
SBIT( T1IE , 0xB9 ) /* Timer 1 Interrupt Enable */
SBIT( DMAIE , 0xB8 ) /* DMA Transfer Interrupt Enable */
/* IRCON */
SBIT( STIF , 0xC7 ) /* Sleep Timer Interrupt Flag */
SBIT( _IRCON6 , 0xC6 ) /* not used */
SBIT( P0IF , 0xC5 ) /* Port 0 Interrupt Flag */
SBIT( T4IF , 0xC4 ) /* Timer 4 Interrupt Flag */
SBIT( T3IF , 0xC3 ) /* Timer 3 Interrupt Flag */
SBIT( T2IF , 0xC2 ) /* Timer 2 Interrupt Flag */
SBIT( T1IF , 0xC1 ) /* Timer 1 Interrupt Flag */
SBIT( DMAIF , 0xC0 ) /* DMA Complete Interrupt Flag */
/* PSW */
SBIT( CY , 0xD7 ) /* Carry Flag */
SBIT( AC , 0xD6 ) /* Auxiliary Carry Flag */
SBIT( F0 , 0xD5 ) /* User-Defined */
SBIT( RS1 , 0xD4 ) /* Register Bank Select 1 */
SBIT( RS0 , 0xD3 ) /* Register Bank Select 0 */
SBIT( OV , 0xD2 ) /* Overflow Flag */
SBIT( F1 , 0xD1 ) /* User-Defined */
SBIT( P , 0xD0 ) /* Parity Flag */
/* TIMIF */
SBIT( _TIMIF7 , 0xDF ) /* not used */
SBIT( OVFIM , 0xDE ) /* Timer 1 Overflow Interrupt Mask */
SBIT( T4CH1IF , 0xDD ) /* Timer 4 Channel 1 Interrupt Flag */
SBIT( T4CH0IF , 0xDC ) /* Timer 4 Channel 0 Interrupt Flag */
SBIT( T4OVFIF , 0xDB ) /* Timer 4 Overflow Interrupt Flag */
SBIT( T3CH1IF , 0xDA ) /* Timer 3 Channel 1 Interrupt Flag */
SBIT( T3CH0IF , 0xD9 ) /* Timer 3 Channel 0 Interrupt Flag */
SBIT( T3OVFIF , 0xD8 ) /* Timer 3 Overflow Interrupt Flag */
/* IRCON2 */
SBIT( _IRCON27 , 0xEF ) /* not used */
SBIT( _IRCON26 , 0xEE ) /* not used */
SBIT( _IRCON25 , 0xED ) /* not used */
SBIT( WDTIF , 0xEC ) /* Watchdog Timer Interrupt Flag */
SBIT( P1IF , 0xEB ) /* Port 1 Interrupt Flag */
SBIT( UTX1IF , 0xEA ) /* USART1 TX Interrupt Flag */
SBIT( UTX0IF , 0xE9 ) /* USART0 TX Interrupt Flag */
SBIT( P2IF , 0xE8 ) /* Port 2 Interrupt Flag */
/* ------------------------------------------------------------------------------------------------
* Xdata Radio Registers
* ------------------------------------------------------------------------------------------------
*/
#define _XREGDF00 XREG( 0xDF00 ) /* reserved */
#define _XREGDF01 XREG( 0xDF01 ) /* reserved */
#define MDMCTRL0H XREG( 0xDF02 ) /* Modem Control 0 High Byte */
#define MDMCTRL0L XREG( 0xDF03 ) /* Modem Control 0 Low Byte */
#define MDMCTRL1H XREG( 0xDF04 ) /* Modem Control 1 High Byte */
#define MDMCTRL1L XREG( 0xDF05 ) /* Modem Control 1 Low Byte */
#define RSSIH XREG( 0xDF06 ) /* RSSI and CCA Status and Control High Byte */
#define RSSIL XREG( 0xDF07 ) /* RSSI and CCA Status and Control Low Byte */
#define SYNCWORDH XREG( 0xDF08 ) /* Synchronization and Control High Byte */
#define SYNCWORDL XREG( 0xDF09 ) /* Synchronization and Control Low Byte */
#define TXCTRLH XREG( 0xDF0A ) /* Transmit Control High Byte */
#define TXCTRLL XREG( 0xDF0B ) /* Transmit Control Low Byte */
#define RXCTRL0H XREG( 0xDF0C ) /* Receive Control 0 High Byte */
#define RXCTRL0L XREG( 0xDF0D ) /* Receive Control 0 Low Byte */
#define RXCTRL1H XREG( 0xDF0E ) /* Receive Control 1 High Byte */
#define RXCTRL1L XREG( 0xDF0F ) /* Receive Control 1 Low Byte */
#define FSCTRLH XREG( 0xDF10 ) /* Frequency Synthesizer Control and Status High Byte */
#define FSCTRLL XREG( 0xDF11 ) /* Frequency Synthesizer Control and Status Low Byte */
#define CSPX XREG( 0xDF12 ) /* CSMA/CA Strobe Processor X Data Register */
#define CSPY XREG( 0xDF13 ) /* CSMA/CA Strobe Processor Y Data Register */
#define CSPZ XREG( 0xDF14 ) /* CSMA/CA Strobe Processor Z Data Register */
#define CSPCTRL XREG( 0xDF15 ) /* CSMA/CA Strobe Processor CPU Control Input */
#define CSPT XREG( 0xDF16 ) /* CSMA/CA Strobe Processor T Data Register */
#define RFPWR XREG( 0xDF17 ) /* Radio Power */
#define _XREGDF18 XREG( 0xDF18 ) /* reserved */
#define _XREGDF19 XREG( 0xDF19 ) /* reserved */
#define _XREGDF1A XREG( 0xDF1A ) /* reserved */
#define _XREGDF1B XREG( 0xDF1B ) /* reserved */
#define _XREGDF1C XREG( 0xDF1C ) /* reserved */
#define _XREGDF1D XREG( 0xDF1D ) /* reserved */
#define _XREGDF1E XREG( 0xDF1E ) /* reserved */
#define _XREGDF1F XREG( 0xDF1F ) /* reserved */
#define FSMTCH XREG( 0xDF20 ) /* Finite State Machine Time Constants High Byte */
#define FSMTCL XREG( 0xDF21 ) /* Finite State Machine Time Constants Low Byte */
#define MANANDH XREG( 0xDF22 ) /* Manual Signal AND Override High Byte */
#define MANANDL XREG( 0xDF23 ) /* Manual Signal AND Override Low Byte */
#define MANORH XREG( 0xDF24 ) /* Manual Signal OR Override High Byte */
#define MANORL XREG( 0xDF25 ) /* Manual Signal OR Override High Byte */
#define AGCCTRLH XREG( 0xDF26 ) /* AGC Control High Byte */
#define AGCCTRLL XREG( 0xDF27 ) /* AGC Control Low Byte */
#define _XREGDF28 XREG( 0xDF28 ) /* reserved */
#define _XREGDF29 XREG( 0xDF29 ) /* reserved */
#define _XREGDF2A XREG( 0xDF2A ) /* reserved */
#define _XREGDF2B XREG( 0xDF2B ) /* reserved */
#define _XREGDF2C XREG( 0xDF2C ) /* reserved */
#define _XREGDF2D XREG( 0xDF2D ) /* reserved */
#define _XREGDF2E XREG( 0xDF2E ) /* reserved */
#define _XREGDF2F XREG( 0xDF2F ) /* reserved */
#define _XREGDF30 XREG( 0xDF30 ) /* reserved */
#define _XREGDF31 XREG( 0xDF31 ) /* reserved */
#define _XREGDF32 XREG( 0xDF32 ) /* reserved */
#define _XREGDF33 XREG( 0xDF33 ) /* reserved */
#define _XREGDF34 XREG( 0xDF34 ) /* reserved */
#define _XREGDF35 XREG( 0xDF35 ) /* reserved */
#define _XREGDF36 XREG( 0xDF36 ) /* reserved */
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