?? jishixianshi.sim.rpt
字號:
; |JISHIXIANSHI|Mux16~19 ; |JISHIXIANSHI|Mux16~19 ; combout ;
; |JISHIXIANSHI|Mux3~4 ; |JISHIXIANSHI|Mux3~4 ; combout ;
; |JISHIXIANSHI|Mux2~37 ; |JISHIXIANSHI|Mux2~37 ; combout ;
; |JISHIXIANSHI|Mux2~38 ; |JISHIXIANSHI|Mux2~38 ; combout ;
; |JISHIXIANSHI|Mux2~39 ; |JISHIXIANSHI|Mux2~39 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|6~25 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|6~25 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|45~14 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|45~14 ; combout ;
; |JISHIXIANSHI|CNT4[1]~20 ; |JISHIXIANSHI|CNT4[1]~20 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|7~25 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|7~25 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst9|7~5 ; |JISHIXIANSHI|JISHU:u1|74160:inst9|7~5 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst9|8~21 ; |JISHIXIANSHI|JISHU:u1|74160:inst9|8~21 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst9|13 ; |JISHIXIANSHI|JISHU:u1|74160:inst9|13 ; combout ;
; |JISHIXIANSHI|CNT4[0]~21 ; |JISHIXIANSHI|CNT4[0]~21 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst9|6~2 ; |JISHIXIANSHI|JISHU:u1|74160:inst9|6~2 ; combout ;
; |JISHIXIANSHI|SG[0] ; |JISHIXIANSHI|SG[0] ; padio ;
; |JISHIXIANSHI|SG[1] ; |JISHIXIANSHI|SG[1] ; padio ;
; |JISHIXIANSHI|SG[2] ; |JISHIXIANSHI|SG[2] ; padio ;
; |JISHIXIANSHI|SG[3] ; |JISHIXIANSHI|SG[3] ; padio ;
; |JISHIXIANSHI|SG[4] ; |JISHIXIANSHI|SG[4] ; padio ;
; |JISHIXIANSHI|SG[5] ; |JISHIXIANSHI|SG[5] ; padio ;
; |JISHIXIANSHI|SG[6] ; |JISHIXIANSHI|SG[6] ; padio ;
; |JISHIXIANSHI|SG1[0] ; |JISHIXIANSHI|SG1[0] ; padio ;
; |JISHIXIANSHI|SG1[1] ; |JISHIXIANSHI|SG1[1] ; padio ;
; |JISHIXIANSHI|SG1[2] ; |JISHIXIANSHI|SG1[2] ; padio ;
; |JISHIXIANSHI|SG1[3] ; |JISHIXIANSHI|SG1[3] ; padio ;
; |JISHIXIANSHI|BT[0] ; |JISHIXIANSHI|BT[0] ; padio ;
; |JISHIXIANSHI|BT[1] ; |JISHIXIANSHI|BT[1] ; padio ;
; |JISHIXIANSHI|BT[2] ; |JISHIXIANSHI|BT[2] ; padio ;
; |JISHIXIANSHI|BT[3] ; |JISHIXIANSHI|BT[3] ; padio ;
; |JISHIXIANSHI|clk1 ; |JISHIXIANSHI|clk1~corein ; combout ;
; |JISHIXIANSHI|CLK0 ; |JISHIXIANSHI|CLK0~corein ; combout ;
; |JISHIXIANSHI|CLK0~clkctrl ; |JISHIXIANSHI|CLK0~clkctrl ; outclk ;
; |JISHIXIANSHI|clk1~clkctrl ; |JISHIXIANSHI|clk1~clkctrl ; outclk ;
+------------------------------------------+------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-------------------------------------------+-------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------+-------------------------------------------+------------------+
; |JISHIXIANSHI|JISHU:u1|74160:inst4|6 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|6 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|6 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|6 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|7 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|7 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|7 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|7 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|8 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|8 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|8 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|8 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|8 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|8 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|9 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|9 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|9 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|9 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|9 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|9 ; regout ;
; |JISHIXIANSHI|Mux15~28 ; |JISHIXIANSHI|Mux15~28 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|6~29 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|6~29 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|45~14 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|45~14 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|6~33 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|6~33 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|7~29 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|7~29 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|50~11 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|50~11 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|50~12 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|50~12 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|7~33 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|7~33 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|8~25 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|8~25 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|8~29 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|8~29 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|8~33 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|8~33 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|13~121 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|13~121 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|13~111 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|13~111 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|13~131 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|13~131 ; combout ;
; |JISHIXIANSHI|SG1[4] ; |JISHIXIANSHI|SG1[4] ; padio ;
; |JISHIXIANSHI|SG1[5] ; |JISHIXIANSHI|SG1[5] ; padio ;
; |JISHIXIANSHI|SG1[6] ; |JISHIXIANSHI|SG1[6] ; padio ;
+-------------------------------------------+-------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-------------------------------------------+-------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------+-------------------------------------------+------------------+
; |JISHIXIANSHI|JISHU:u1|74160:inst4|6 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|6 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|6 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|6 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|7 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|7 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|7 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|7 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|7 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|7 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|8 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|8 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|8 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|8 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|8 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|8 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|9 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|9 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|9 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|9 ; regout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|9 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|9 ; regout ;
; |JISHIXIANSHI|Mux15~28 ; |JISHIXIANSHI|Mux15~28 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|6~29 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|6~29 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|45~14 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|45~14 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|6~33 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|6~33 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|7~29 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|7~29 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|50~11 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|50~11 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|50~12 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|50~12 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|7~33 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|7~33 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|8~25 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|8~25 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|8~29 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|8~29 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|8~33 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|8~33 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst4|13~121 ; |JISHIXIANSHI|JISHU:u1|74160:inst4|13~121 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst3|13~111 ; |JISHIXIANSHI|JISHU:u1|74160:inst3|13~111 ; combout ;
; |JISHIXIANSHI|JISHU:u1|74160:inst6|13~131 ; |JISHIXIANSHI|JISHU:u1|74160:inst6|13~131 ; combout ;
; |JISHIXIANSHI|SG1[4] ; |JISHIXIANSHI|SG1[4] ; padio ;
; |JISHIXIANSHI|SG1[5] ; |JISHIXIANSHI|SG1[5] ; padio ;
; |JISHIXIANSHI|SG1[6] ; |JISHIXIANSHI|SG1[6] ; padio ;
+-------------------------------------------+-------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sat Mar 14 09:15:58 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off JISHIXIANSHI -c JISHIXIANSHI
Info: Using vector source file "G:/EDA/JISHIXIANSHI/JISHIXIANSHI.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 67.44 %
Info: Number of transitions in simulation is 4717
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 101 megabytes of memory during processing
Info: Processing ended: Sat Mar 14 09:16:01 2009
Info: Elapsed time: 00:00:03
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