+----------------------------------+-----------------+------------------------+---------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Total logic elements                        ; 166      ;
;     -- Combinational with no register       ; 96       ;
;     -- Register only                        ; 26       ;
;     -- Combinational with a register        ; 44       ;
;                                             ;          ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 46       ;
;     -- 3 input functions                    ; 22       ;
;     -- 2 input functions                    ; 69       ;
;     -- 1 input functions                    ; 3        ;
;     -- 0 input functions                    ; 0        ;
;         -- Combinational cells for routing  ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 108      ;
;     -- arithmetic mode                      ; 58       ;
;     -- qfbk mode                            ; 0        ;
;     -- register cascade mode                ; 0        ;
;     -- synchronous clear/load mode          ; 0        ;
;     -- asynchronous clear/load mode         ; 0        ;
;                                             ;          ;
; Total registers                             ; 70       ;
; Total logic cells in carry chains           ; 61       ;
; I/O pins                                    ; 14       ;
; Maximum fan-out node                        ; clk_100M ;
; Maximum fan-out                             ; 44       ;
; Total fan-out                               ; 500      ;
; Average fan-out                             ; 2.78     ;
+---------------------------------------------+----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |clock                     ; 166 (166)   ; 70           ; 0          ; 14   ; 0            ; 96 (96)      ; 26 (26)           ; 44 (44)          ; 61 (61)         ; 0 (0)      ; |clock              ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 70    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |clock|led_buf[2]          ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |clock|min[4]              ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |clock|min[8]              ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |clock|min[13]             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |clock ;
+----------------+----------+-------------------------------------------+
; Parameter Name ; Value    ; Type                                      ;
+----------------+----------+-------------------------------------------+
; countful       ; 49999999 ; Integer                                   ;
; counterfull_1k ; 49999    ; Integer                                   ;
+----------------+----------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Mar 05 19:27:52 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.v
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Warning (10235): Verilog HDL Always Construct warning at clock.v(91): variable "count2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock.v(91): variable "clk_1hz" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Duplicate registers merged to single register
    Info: Duplicate register "count1[0]" merged to single register "count[0]"
    Info: Duplicate register "count1[1]" merged to single register "count[1]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "count1[2]" merged to single register "count[2]"
    Info: Duplicate register "count1[3]" merged to single register "count[3]"
Info: Implemented 180 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 13 output pins
    Info: Implemented 166 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Mar 05 19:27:55 2009
    Info: Elapsed time: 00:00:03