?? turbo_code_punc.mdl
字號:
}
Line {
SrcBlock "Buffer"
SrcPort 1
DstBlock "Frame Status Conversion"
DstPort 1
}
Line {
SrcBlock "Frame Status Conversion"
SrcPort 1
DstBlock "Mean"
DstPort 1
}
Line {
SrcBlock "Zero-Order\nHold"
SrcPort 1
DstBlock "Error Rate Calculation1"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Error Rate Calculation1"
DstPort 3
}
Line {
SrcBlock "Mean"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Signal From\nWorkspace"
SrcPort 1
Points [40, 0]
DstBlock "Mean"
DstPort 2
}
}
}
Block {
BlockType SubSystem
Name "receiver_front_end"
Ports [1, 2]
Position [475, 455, 515, 515]
Orientation "left"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "receiver_front_end"
Location [130, 145, 893, 622]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [15, 53, 45, 67]
IconDisplay "Port number"
}
Block {
BlockType Gain
Name "Gain"
Position [105, 45, 125, 75]
Gain "2/Variance"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
SampleTime "1"
}
Block {
BlockType Reference
Name "Insert Zero"
Ports [1, 1]
Position [255, 37, 325, 83]
SourceBlock "commsequence2/Insert Zero"
SourceType "Insert Zero"
insertZeroVector "[1 1 0 1 0 1].'"
}
Block {
BlockType Reference
Name "Interlacer1"
Ports [2, 1]
Position [485, 218, 565, 267]
Orientation "left"
NamePlacement "alternate"
SourceBlock "commsequence2/Interlacer"
SourceType "Interlacer"
}
Block {
BlockType Reference
Name "Interlacer2"
Ports [2, 1]
Position [325, 383, 405, 432]
Orientation "left"
NamePlacement "alternate"
SourceBlock "commsequence2/Interlacer"
SourceType "Interlacer"
}
Block {
BlockType Reference
Name "Matrix\nDeinterleaver"
Ports [1, 1]
Position [390, 27, 460, 93]
SourceBlock "commblkintrlv2/Matrix\nDeinterleaver"
SourceType "Matrix Deinterleaver"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Nrows "3"
Ncols "Len"
}
Block {
BlockType Reference
Name "Multiport\nSelector2"
Ports [1, 3]
Position [525, 26, 560, 94]
ShowName off
SourceBlock "dspindex/Multiport\nSelector"
SourceType "Multiport Selector"
rowsOrCols "Rows"
idxCellArray "{1:Len, Len+1:2*Len, 2*Len+1:3*Len} "
idxErrMode "Clip Index"
}
Block {
BlockType Reference
Name "Random\nInterleaver1"
Ports [1, 1]
Position [515, 323, 595, 377]
Orientation "left"
SourceBlock "commblkintrlv2/Random\nInterleaver"
SourceType "Random Interleaver"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
N "Len"
seed "Seed"
}
Block {
BlockType ZeroOrderHold
Name "Zero-Order\nHold"
Position [185, 39, 210, 81]
ShowName off
SampleTime "Iter"
}
Block {
BlockType Outport
Name "Out1"
Position [365, 238, 395, 252]
Orientation "left"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out2"
Position [220, 403, 250, 417]
Orientation "left"
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Multiport\nSelector2"
SrcPort 1
Points [125, 0; 0, 190]
Branch {
DstBlock "Interlacer1"
DstPort 1
}
Branch {
Points [25, 0; 0, 120]
DstBlock "Random\nInterleaver1"
DstPort 1
}
}
Line {
SrcBlock "Multiport\nSelector2"
SrcPort 2
Points [100, 0; 0, 195]
DstBlock "Interlacer1"
DstPort 2
}
Line {
SrcBlock "Random\nInterleaver1"
SrcPort 1
Points [-50, 0; 0, 45]
DstBlock "Interlacer2"
DstPort 1
}
Line {
SrcBlock "Multiport\nSelector2"
SrcPort 3
Points [65, 0; 0, 340]
DstBlock "Interlacer2"
DstPort 2
}
Line {
SrcBlock "Zero-Order\nHold"
SrcPort 1
DstBlock "Insert Zero"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Interlacer1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Interlacer2"
SrcPort 1
DstBlock "Out2"
DstPort 1
}
Line {
SrcBlock "Matrix\nDeinterleaver"
SrcPort 1
DstBlock "Multiport\nSelector2"
DstPort 1
}
Line {
SrcBlock "Insert Zero"
SrcPort 1
DstBlock "Matrix\nDeinterleaver"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
DstBlock "Zero-Order\nHold"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "turbo_decoder"
Ports [2, 1]
Position [325, 455, 365, 515]
Orientation "left"
ForegroundColor "white"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "turbo_decoder"
Location [2, 97, 1022, 709]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [400, 15, 430, 30]
Orientation "down"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "In2"
Position [270, 233, 300, 247]
Orientation "left"
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "APP Decoder"
Ports [2, 2]
Position [353, 110, 442, 185]
Orientation "down"
SourceBlock "commcnvcod2/APP Decoder"
SourceType "APP Decoder"
trellis "trellis"
termMethod "Truncated"
algorithm "Max*"
maxStarNumScaleBits "3"
}
Block {
BlockType Reference
Name "APP Decoder1"
Ports [2, 2]
Position [170, 179, 245, 261]
Orientation "left"
NamePlacement "alternate"
SourceBlock "commcnvcod2/APP Decoder"
SourceType "APP Decoder"
trellis "trellis"
termMethod "Truncated"
algorithm "Max*"
maxStarNumScaleBits "3"
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [175, 68, 220, 102]
ShowName off
SourceBlock "dspsigops/Delay"
SourceType "Delay"
dly_unit "Samples"
delay "Len"
ic_detail "off"
dif_ic_for_ch "off"
dif_ic_for_dly "off"
ic "0"
reset_popup "None"
}
Block {
BlockType DiscretePulseGenerator
Name "Discrete Pulse\nGenerator"
Ports [0, 1]
Position [215, 110, 235, 130]
ShowName off
Period "Iter"
PulseWidth "Iter-1"
PhaseDelay "1"
}
Block {
BlockType Product
Name "Frame Reset"
Ports [2, 1]
Position [275, 76, 320, 109]
ShowName off
RndMeth "Floor"
}
Block {
BlockType SubSystem
Name "Hard Decision1"
Ports [1, 1]
Position [80, 31, 120, 69]
Orientation "left"
NamePlacement "alternate"
ShowName off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
MaskType "Hard Decision"
MaskDescription "Likelihood to binary transformation.\n"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "Hard Decision1"
Location [557, 301, 1057, 642]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "Lin"
Position [170, 130, 200, 140]
NamePlacement "alternate"
IconDisplay "Port number"
}
Block {
BlockType Constant
Name "Constant"
Position [105, 135, 145, 165]
ShowName off
Value "0"
VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator"
Position [245, 125, 280, 160]
ShowName off
}
Block {
BlockType Outport
Name "0/1"
Position [350, 140, 380, 150]
NamePlacement "alternate"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Relational\nOperator"
DstPort 2
}
Line {
SrcBlock "Lin"
SrcPort 1
DstBlock "Relational\nOperator"
DstPort 1
}
Line {
SrcBlock "Relational\nOperator"
SrcPort 1
DstBlock "0/1"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "Random\nDeinterleaver"
Ports [1, 1]
Position [78, 105, 132, 185]
Orientation "up"
SourceBlock "commblkintrlv2/Random\nDeinterleaver"
SourceType "Random Deinterleaver"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
N "Len"
seed "Seed"
}
Block {
BlockType Reference
Name "Random\nInterleaver3"
Ports [1, 1]
Position [290, 172, 340, 228]
Orientation "left"
NamePlacement "alternate"
SourceBlock "commblkintrlv2/Random\nInterleaver"
SourceType "Random Interleaver"
ShowPortLabels "on"
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