?? ram_even.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RAM_Even is
generic (
WIDTH : integer;
AW : integer);
port (
AddrxDIE : in std_logic_vector( AW-1 downto 0);
WExSIE : in std_logic;
EnxSIE : in std_logic;
WClkxCI : in std_logic;
DinxDIE : in std_logic_vector( WIDTH-1 downto 0);
DoutxDOE : out std_logic_vector( WIDTH-1 downto 0));
end RAM_Even;
architecture behav of RAM_Even is
type ram_type is array (0 to 1023) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
process (AddrxDIE)
begin
DoutxDOE <= tmp_ram(conv_integer(AddrxDIE));
end process;
process (WClkxCI, WExSIE)
begin
if (WClkxCI 'event and WClkxCI ='1') then
if WExSIE = '1' then
if EnxSIE = '1' then
tmp_ram(conv_integer(AddrxDIE)) <= DinxDIE;
end if;
end if;
end if;
end process;
end behav;
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