?? ram_odd.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RAM_Odd is
generic (
WIDTH : integer;
AW : integer);
port (
AddrxDIO : in std_logic_vector( AW-1 downto 0);
WExSIO : in std_logic;
EnxSIO : in std_logic;
WClkxCI : in std_logic;
DinxDIO : in std_logic_vector( WIDTH-1 downto 0);
DoutxDOO : out std_logic_vector( WIDTH-1 downto 0));
end RAM_Odd;
architecture behav of RAM_Odd is
type ram_type is array (0 to 1023) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
process (AddrxDIO)
begin
DoutxDOO <= tmp_ram(conv_integer(AddrxDIO));
end process;
process (WClkxCI, WExSIO)
begin
if (WClkxCI 'event and WClkxCI ='1') then
if WExSIO = '1' then
if EnxSIO = '1' then
tmp_ram(conv_integer(AddrxDIO)) <= DinxDIO;
end if;
end if;
end if;
end process;
end behav;
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