//           僒儞僾儖僾儘僌儔儉 ERAMoffset.eve
//
// 奜晅偗儊儌儕乕傾僪儗僗曗惓儗僕僗僞 OFST 傪巊梡偟偨僾儘僌儔儉偱偡丅
// SDI0 偺 Lch 偵擖椡偝傟偨怣崋偵懳偟偰丄48000 僒儞僾儖僨傿儗僀偝
// 偣偨怣崋傪 SDO0 偺 Lch 偵丄48000+OFST 僒儞僾儖僨傿儗僀偝偣偨怣崋
// 傪 SDO0 偺 Rch 偵弌椡偟偰偄傑偡丅
//
// SDO0 偺 L/Rch 埲奜偺僠儍儞僱儖偼偡傋偰 0 弌椡偱偡丅
//
// 僔僌僫儖僼儘乕 ERAMoffset.pdf 傪嶲徠偟偰偔偩偝偄丅
//
// 偙偺僾儘僌儔儉傪傾僙儞僽儔 EveAsm.exe 偱傾僙儞僽儖偡傞偙偲偵傛傝
// ERAMoffset.datEve 偑嶌惉偝傟傑偡丅
//
// 側偍丄奜晅偗儊儌儕乕偵 DRAM 傪巊梡偟偨応崌偼丄儕僼儗僢僔儏偺偨傔偺
// 傾僋僙僗偑昁梫偱偡丅
// 4M bit DRAM (262144 word * 16 bit) 偺応崌丄
//    TDat=0     偐傜 TDat=32767  偺斖埻偱嵟掅堦夞
//    TDat=32768 偐傜 TDat=65535  偺斖埻偱嵟掅堦夞
//    TDat=65536 偐傜 TDat=98303  偺斖埻偱嵟掅堦夞
//    TDat=98304 偐傜 TDat=131071 偺斖埻偱嵟掅堦夞
// 偼傾僋僙僗偡傞傛偆偵僾儘僌儔儉傪彂偔昁梫偑偁傝傑偡丅
// 傾僙儞僽儔傪捠偡偙偲偵傛偭偰儕僼儗僢僔儏梡偺僟儈乕傾僋僙僗偑昁梫偐
// 偳偆偐傪妋擣偱偒傑偡丅
//
// -----------------------------------------------------------------
//
//           Sample program  ERAMoffset.eve
//
// This is the program using OFST, the offset register for adjusting external
// memory address.
// SDI0 Lch input signal is delayed by 48000 samples and output from SDO0 Lch.
// SDI0 Lch input signal is also delayed by 48000+OFST samples and output from 
// SDO0 Rch.
//
// The other channels except for SDO0 L/Rch are all zero output.
//
// Refer to the signal flow ERAMoffset.pdf.
//
// ERAMoffset.datEve is assemble from this program by executing EveAsm.exe.
//
// When DRAM is used as external memory, take care that refresh access is needed.
// For example, when 4M bit DRAM (262144 word * 16 bit) is used :
//   at least one access during TDat=0     to TDat=32767.
//   at least one access during TDat=32768 to TDat=65535.
//   at least one access during TDat=65536 to TDat=98303.
//   at least one access during TDat=98304 to TDat=131071.
// is needed to be programmed.
// it is possible to confirm whether dummy access for refresh is needed or not by
// the assembler.



// -----------------------------------------------------------------
// -----------------------------------------------------------------
// -----------------------------------------------------------------

#define ERAM_TYPE DRAM             //奜晅 DRAM 巊梡

//============================================================
//                  EVE Program
//                       ERAMoffset
//============================================================

// COEF define
	CDat	P0.5		(-1, 0x4000);		//

// Inner DATA define
	DAdr	Dtmp		(0);				// temporary 梡

// delay tap
	TDat	TIN			(-1, 0);			// 奜晅偗 memory 梡 delay tap
	TDat	TOUT		(-1, 48000);		//

	TDat	Tdummy1		(-1, 32768);		// DRAM refresh 梡 read address
	TDat	Tdummy2		(-1, 65536);		//
	TDat	Tdummy3		(-1, 98304);		//

//------------------------------------------------------------
//       幚峴僐儅儞僪僽儘僢僋
//  	|   ERAM            |   BUS             |   MAC/JMP   
//------------------------------------------------------------
		;					OFST = $ZERO;		;								// OFST=0 傪 set丅
		;					;					;
		;					;					;
		;					;					;
		wr(TIN);			EW = IN0;			;								// SDI0/L (IN0) 傪 address TIN 傊彂偒崬傒丅
		;					;					;								// wr 柦椷偐傜 6 step wait丅
		;					;					;
		;					;					;
		;					;					;
		;					;					;
		rd(TOUT);			;					;								// address TOUT 傪撉傒弌偟丄ER0 傊 save丅
		put(ER0);			;					;
		;					;					;								// rd 柦椷偐傜 7 step wait丅
		;					;					;
		;					;					;
		;					;					;
		;					;					;
		;					;					ACC0 = ER0 * P0.5;				// ER0 傪 MAC 宱桼偱 OUT0 傊丅
		;					;					;
		;					;					;
		;					;					;
		;					OUT0 = ACC0Ls1;		;								// address TOUT 暘 delay 屻偺抣傪 OUT0 傊 save丅
//---------------------------
		;					OFST = 0x2EE0;		;								// OFST=0x2EE0 (120000) 傪 set丅
		;					;					;
		rd(TOUT);			;					;								// address TOUT+12000 傪撉傒弌偟丄ER0 傊 save丅
		put(ER0);			;					;
		;					;					;								// rd 柦椷偐傜 7 step wait丅
		;					;					;
		;					;					;
		;					;					;
		;					;					;
		;					;					ACC0 = ER0 * P0.5;				// ER0 傪 MAC 宱桼偱 OUT1 傊丅
		;					;					;
		;					;					;
		;					;					;
		;					OUT1 = ACC0Ls1;		;								// address TOUT+12000 暘 delay 屻偺抣傪 OUT1 傊 save丅
//	----------------------------------------------------------------------
		;					OUT2 = $ZERO;		;								// 懠偺 channel 傪 0 clear丅
		;					OUT3 = $ZERO;		;								// 懠偺 channel 傪 0 clear丅
		;					OUT4 = $ZERO;		;								// 懠偺 channel 傪 0 clear丅
		;					OUT5 = $ZERO;		;								// 懠偺 channel 傪 0 clear丅
		;					OUT6 = $ZERO;		;								// 懠偺 channel 傪 0 clear丅
		;					OUT7 = $ZERO;		;								// 懠偺 channel 傪 0 clear丅
//	----------------------------------------------------------------------
		rd(Tdummy1);		;					;								// DRAM refresh 偺偨傔偺 dummy read丅
		put(ER0);			;					;
		;					;					;
		;					;					;
		;					;					;
		;					;					;
		rd(Tdummy2);		;					;								// DRAM refresh 偺偨傔偺 dummy read丅
		put(ER0);			;					;
		;					;					;
		;					;					;
		;					;					;
		;					;					;
		rd(Tdummy3);		;					;								// DRAM refresh 偺偨傔偺 dummy read丅
		put(ER0);			;					;
		;					;					;
		;					;					;
		;					;					;
		;					;					;
//	----------------------------------------------------------------------
		;					MPEND = $0.5;		;								// program 廔椆丅
		;					;					;
		;					;					;