// 
//  Project: Experiment 2.10.7 Use AIC23 via McBSP - Chapter 2 
//  File name: mcbsp.h   
//
//  Description: This is the C header file for aic23 experiment 
//
//  For the book "Real Time Digital Signal Processing: 
//                Implementation and Application, 2nd Ed"
//                By Sen M. Kuo, Bob H. Lee, and Wenshun Tian
//                Publisher: John Wiley and Sons, Ltd
//
//  Tools used: CCS v.2.12.07
//              TMS320VC5510 DSK Rev-C
//

#define McBSP_BASE    0x2800
#define McBSP0_OFFSET 0x0000
#define McBSP1_OFFSET 0x0400
#define McBSP2_OFFSET 0x0800

#define DRR2    0x00  // Data Receive Register 2
#define DRR1    0x01  // Data Receive Register 1
#define DXR2    0x02  // Data Transmit Register 2
#define DXR1    0x03  // Data Transmit Register 1
#define SPCR2   0x04  // Serial Port Control Register 2
#define SPCR1   0x05  // Serial Port Control Register 1
#define RCR2    0x06  // Receive Control Register 2
#define RCR1    0x07  // Receive Control Register 1
#define XCR2    0x08  // Transmit Control Register 2
#define XCR1    0x09  // Transmit Control Register 1
#define SRGR2   0x0A  // Sample Rate Generator Register 2
#define SRGR1   0x0B  // Sample Rate Generator Register 1
#define MCR2    0x0C  // Multi-channel Register 2
#define MCR1    0x0D  // Multi-channel Register 1
#define RCERA   0x0E  // Receive Channel enable Register A
#define RCERB   0x0F  // Receive Channel enable Register B
#define XCERA   0x10  // Transmit Channel enable Register A
#define XCERB   0x11  // Transmit Channel enable Register B
#define PCR     0x12  // Pin Control Register
#define RCERC   0x13  // Receive Channel enable Register C
#define RCERD   0x14  // Receive Channel enable Register D
#define XCERC   0x15  // Transmit Channel enable Register C
#define XCERD   0x16  // Transmit Channel enable Register D
#define RCERE   0x17  // Receive Channel enable Register E
#define RCERF   0x18  // Receive Channel enable Register F
#define XCERE   0x19  // Transmit Channel enable Register E
#define XCERF   0x1A  // Transmit Channel enable Register F
#define RCERG   0x1B  // Receive Channel enable Register G
#define RCERH   0x1C  // Receive Channel enable Register H
#define XCERG   0x1D  // Transmit Channel enable Register G
#define XCERH   0x1E  // Transmit Channel enable Register H


// SPC1 bit definition  
#define CLKSTP_BIT 0x1000      // Clock stop without delay
#define RRDY_BIT   0x0002
#define RRST_BIT   0x0001

// SPC2 bit definition    
#define SOFT_BIT   0x0100
#define FRST_BIT   0x0080
#define GRST_BIT   0x0040
#define XRDY_BIT   0x0002
#define XRST_BIT   0x0001

// XCR1 and XCR2 bit definition 
#define XFRLEN1_BIT   0x0100      // Set as one word per frame
#define XWDLEN1_BIT   0x0040      // Select 16-bit data

// RCR1 bit definition
#define RFRLEN1_BIT   0x0100      // Set as one word per frame
#define RWDLEN1_BIT   0x0040      // Select 16-bit data

// SPGR1 bit definition
#define CLKGDV_BIT    0x0063      // CLKG divide-down value
 
// SRGR2 bit definition
#define CLKSM_BIT     0x2000      // Select cpu clock
#define FPER_BIT      0x0013      // Default to 19 CLKG cycles

// PRC bit definition
#define RIOEN_BIT     0x1000      // Receive I/O enable
#define FSRM_BIT      0x0800      // Transmit frame sync mode set
#define CLKXM_BIT     0x0200      // Clock is master mode for SPI
#define FSRP_BIT      0x0008      // Transimit frame sync active low
#define CLKXP_BIT     0x0002      // Transmit clock at falling edge of CLKR
#define CLKRP_BIT     0x0001      // Receive clock at rising edge of CLKR

// Glabal functions
extern void  mcbsp1CtlTx(ioport volatile unsigned short *reg, short regValue);
extern void  mcbspReset(short mcbspx);
extern short mcbsp2DatTx(short data);
extern void  mcbsp1Init(void);
extern void  mcbsp2Init(void);