Because this configuration uses custom keyboard and mouse drivers, thefile target/h/ugl/config/uglCustom.h must be created from the templatein the same directory.  An excerpt from this file is shown below:\bs  /@ Custom keyboard @/  #ifdef INCLUDE_CUSTOM_KEYBOARD  #define INCLUDE_UGL_INPUT  #define SYS_KEYBOARD_NAME     "/keyboard/0"  /@ Name of the function to create the keyboard device @/  extern STATUS                      ambaKbdDevCreate(char *name);  #define SYS_KEYBOARD_CREATE        ambaKbdDevCreate  /@ Name of the function to initialize the keyboard device @/  extern UGL_INPUT_DEVICE_ID uglAmbaKbdInit (char * name,                                     UGL_EVENT_SERVICE_ID eventServiceId);  #define UGL_KEYBOARD_INIT	   uglPcKbdInit  #endif /@ INCLUDE_CUSTOM_KEYBOARD @/  /@ Custom pointer @/  #ifdef INCLUDE_CUSTOM_POINTER  #ifndef INCLUDE_UGL_INPUT  #define INCLUDE_UGL_INPUT  #endif /@ INCLUDE_UGL_INPUT @/  #define SYS_POINTER_NAME     "/ambaPtr/0"  /@ Name of the function to create the pointer device @/  extern STATUS                      ambaPs2DevCreate(char *name);  #define SYS_POINTER_CREATE	   ambaPs2DevCreate  /@ Name of the function to initialize the pointer device @/  extern UGL_INPUT_DEVICE_ID uglPs2PtrInit (char * name,                                     UGL_EVENT_SERVICE_ID eventServiceId);  #define UGL_POINTER_INIT	   uglPs2PtrInit  #endif /@ INCLUDE_CUSTOM_POINTER @/\beAlso, make sure, IGS is compiled into the ARM libraries.The 'igs' directory may need to be added to the Makefile'target/src/ugl/driver/graphics/Makefile' as follows:\bs  ifeq ($(CPU), ARMARCH4)      CPU_SUBDIRS = arm igs  endif  ifeq ($(CPU), ARMARCH5)      CPU_SUBDIRS = arm igs  endif\beThe macro USE_BSP_API must be defined.  This can be done by inserting'CPU==ARMARCH4' in the file target/h/ugl/driver/graphics/igs/udigs.h asfollows:\bs  #if ((CPU == MIPS32) || (CPU == MIPS64) || (CPU == ARMARCH4) \    || (CPU == ARMARCH5))  #define USE_BSP_API  #endif\beHARDWARE DETAILS\sh DevicesThe device drivers included are:    primeCellSio.c - PrimeCell UART driver.If Flash support is configured then the following drivers are included:   nvRamToFlash.c - NVRAM-to-Flash memory library\sh Shared memoryThis BSP has not been tested with shared memory, and there is noBSP-specific support for test-and-set primitives.  The vxTas()primitive is provided in the architecture-specific code to allow accessto the ARM SWPB instruction.  For further information, see the vxTas()reference entry.\sh Interrupts22 interrupt levels are provided:    0 Soft interrupt    1 UART 0    2 UART 1    3 Keyboard    4 Mouse    5 Timer 0    6 Timer 1    7 Timer 2    8 Real time clock    9 Logic module 0   10 Logic module 1   11 Logic module 2   12 Logic module 3   13 PCI bus (INTA#)   14 PCI bus (INTB#)   15 PCI bus (INTC#)   16 PCI bus (INTD#)   17 V3 PCI bridge   18 CompactPCI auxiliary interrupt (DEG#)   19 CompactPCI auxiliary interrupt (ENUM#)   20 PCI local bus fault   21 External AutoPCOnly interrupt levels 1, 2, 5, 6, 13, 14, 15 and 16 are used by defaultin this BSP.  Interrupt connection, enabling and disabling areperformed using the standard intArchLib routines.  The interruptcontroller driver is provided in ambaIntrCtl.c.\sh Serial ConfigurationThere are two serial ports on the board, provided by two PrimeCell UARTs.The default configuration is 9600 baud, 8 data bits, no parity, 1 stopbit.The driver code in primecellSio.c/.h is a modified version of thestandard VxWorks ambaSio driver.  Documentation for the PrimeCell UARTis on the ARM web site.The two main differences are as follows:The PrimeCell SIO has five separate interrupt signal lines.  Four ofthese correspond to different types of interrupt; the fifth is acombined signal, which is used on the Integrator to provide a singleinterrupt source for each UART.There are two separate interrupt signals for received data: one isgenerated when the received buffer is more than half full; the otherwhen no data is received for 32 UART clocks.\sh SCSI ConfigurationThis BSP does not support SCSI.\sh Network ConfigurationThis BSP provides network support for PCI Dec 21x4x and Intel 8255xnetwork cards.\sh VME AccessThe board is a standalone board: VME is not supported.\sh PCI AccessThis BSP supports the PCI bus and has been tested with networkexpansion cards.  PCI to PCI bridge functionality is not implemented.\sh Boot DevicesBy default, VxWorks is booted on this board by running the boot ROMimage from flash memory and loading the VxWorks kernel via the networkdriver.\sh Power ManagmentSupport is provided for power management.  This allows the core to sleepfor periods of up to 700 ms.  The maximum sleep period is limited bythe timer hardware.  If enabled, power managmenet uses Timer-2.  Powermanagement turns the processor clock off when the system is otherwise idle,but keeps the system timer interrupt clock running.  The system goes intoa low power "sleep" mode until an interrupt wakes the system up.  Powermanagement reschedules the system timer based on the time to the nextscheduled system event.  When the system wakes up, it recomputes systemtime and adjusts the tick count.Power managment is enabled in config.h by defining INCLUDE_POWER_MGMT_CPU_BSP_SUPPORT.SPECIAL CONSIDERATIONS\sh CPU Speed/TimersBoth the system timer and sleep timer are derived from the onboard 24 mhzreference clock.  For the system timer, this clock rate is divided by 16.During extened sleep periods, the timer prescaller is set to 256.  Asnoted in the BSP developer's guide, selecting a tick rate that is not amultiple of the timer clock reference will result in tick period inaccuracy.If power managmenet is enabled, it is important to divide the system clockby 256 before selecting a tick rate.  Otherwise, an accurate tick rate canbe obtained by dividing the 24 mhz reference by 16.All clocks are derived from various VCOs and dividers, which can bemodified under software control.  Clock values are read throuh thecoprocessor are set according to the header fitted (cf. romInit.s).\sh Special routinesThe routine sysLedsReadWrite() is used to control the LEDs on theboard.  Use of the LEDs is mutually exclusive with use of the parallelport due to a restriction in the hardware.  For further information,see the reference entry for this routine.\sh Divide by Zero ExceptionThe ARM architecture does not provide for an integer divide by zeroexception.  Consequently, no exception is generated when an integerdivide by zero operation is performed programmatically.\sh Multiple core module supportSupport is provided for only one core module.\sh BSP Validation Test SuiteThe following BSP VTS test cases are expected to fail:- tmSysClock.tstSysClkDisable fails when compiled with gnu due to timeout\sh nvRamTestIf you get strange fatal errors (looks like the test stopped running) duringnvRamTests, try increasing pauseTimeDefault to 50 and cmdResponseTimeout to100 in /vxtest/src/scripts/runVxTest.exp. It may help.BOARD LAYOUTThe diagrams below show the relevant jumpers for VxWorksconfiguration.\bs______________________________________________________________________________|               +---+ +---+ +---+ +---+    J15                               ||         LOGIC | U | | U | | U | | U |    +-+                             +-+|          +-+  |11 | |12 | |13 | |14 |    | |                          J21| ||+-------+ | |  +---+ +---+ +---+ +---+    | |                             | ||| J12   + | |  +---+ +---+ +---+ +---+    | |                             +-+|+-------+ | |  | U | | U | | U | | U |    | |                       S3   S2 ||          +-+  |15 | |16 | |17 | |18 |    | |                               ||               +---+ +---+ +---+ +---+    | |                               ||               +-----+                    | |                               ||           U34 |SRAM |   ----EXPM----     +-+                               ||               +-----+             +---+                                    ||--+            +-----+             |U19|                                    ||  |ALPHA   U35 |SRAM |             +---+                                    ||  |DISPLAY     +-----+           +-----+                                    ||--+                              | V3  |                                    ||                                 +-----+                                    ||    +----------------------------+       +-+ +-+ +-+                        ||    |                            |       | | | | | |                       +--+|    |                            |       |P| |P| |P|                       |C ||    |               +-------+    |       |C| |C| |C|                       |O ||    |               |  FPGA |    |       |I| |I| |I|                       |M |+-+  | +------+      |       |    |       | | | | | |                       |P ||A|  | |  CPU |      +-------+    |       |S| |S| |S|                       |A ||T|  | |      |                   |       |L| |L| |L|                       |C ||X|  | +----- +                   |       |O| |O| |O|                       |T |+-+  |                            |       |T| |T| |T|            +--------+ |  ||    +----------------------------+       | | | | | |            | PCI/PCI| |P ||KBD                                      +-+ +-+ +-+            | Bridge | |C |+--+      SERIAL SERIAL                   J9  J10 J11            +--------+ |I ||  |  S1  +----+ +----+                                                     +--+|__|______|    |_|    |_____________________    ______________________________|\be    Key:    S1    4 pole DIL switch    S2    Reset button    S3    Standby button    U11.. Flash memory    U19   Boot ROM    J15   Logic module connector (EXPA)    EXPM  External bus interface connector    V3    System bus - PCI bridgeSEE ALSO\tb Tornado User's Guide: Getting Started,\tb VxWorks Programmer's Guide: Configuration.BIBLIOGRAPHY\tb ARM Integrator/AP User Guide ,\tb ARM Integrator/CM7TDMI User Guide ,\tb ARM Integrator/CM720T User Guide ,\tb ARM Integrator/CM740T User Guide ,\tb ARM Integrator/CM920T User Guide ,\tb ARM Integrator/CM940T User Guide ,\tb ARM Integrator/CM926EJ-S, CM946E-S, CM966E-ST User Guide ,\tb ARM Integrator/CM9x6ES Datasheet ,\tb ARM Architecture Reference Manual ,\tb ARM 7TDMI Data Sheet ,\tb ARM 720T Data Sheet ,\tb ARM 740T Data Sheet ,\tb ARM 920T Technical Reference Manual ,\tb ARM 926EJ-S Technical Reference Manual ,\tb ARM 940T Technical Reference Manual ,\tb ARM 966ES Technical Reference Manual ,\tb ARM Reference Peripherals Specification .