?? lpc2300.s
字號:
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
; LDR PC, IRQ_Addr
LDR PC, [PC, #-0x0120] ; Vector from VicVectAddr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
; Clock Setup ------------------------------------------------------------------
IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
LDR R0, =SCB_BASE
MOV R1, #0xAA
MOV R2, #0x55
; Configure and Enable PLL
LDR R3, =SCS_Val ; Enable main oscillator
STR R3, [R0, #SCS_OFS]
IF (SCS_Val:AND:OSCEN) != 0
OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize
ANDS R3, R3, #OSCSTAT
BEQ OSC_Loop
ENDIF
LDR R3, =CLKSRCSEL_Val ; Select PLL source clock
STR R3, [R0, #CLKSRCSEL_OFS]
LDR R3, =PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
IF (CLKSRCSEL_Val:AND:3) != 2
; Wait until PLL Locked (if source is not RTC oscillator)
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
ELSE
; Wait at least 200 cycles (if source is RTC oscillator)
MOV R3, #(200/4)
PLL_Loop SUBS R3, R3, #1
BNE PLL_Loop
ENDIF
M_N_Lock LDR R3, [R0, #PLLSTAT_OFS]
LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N)
AND R3, R3, R4
LDR R4, =PLLCFG_Val
EORS R3, R3, R4
BNE M_N_Lock
; Setup CPU clock divider
MOV R3, #CCLKCFG_Val
STR R3, [R0, #CCLKCFG_OFS]
; Setup USB clock divider
LDR R3, =USBCLKCFG_Val
STR R3, [R0, #USBCLKCFG_OFS]
; Setup Peripheral Clock
LDR R3, =PCLKSEL0_Val
STR R3, [R0, #PCLKSEL0_OFS]
LDR R3, =PCLKSEL1_Val
STR R3, [R0, #PCLKSEL1_OFS]
; Switch to PLL Clock
MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
LDR R4, =PCONP_Val ; Enable Peripheral Clocks
STR R4, [R0, #PCONP_OFS]
ENDIF ; CLOCK_SETUP
; Setup Memory Accelerator Module ----------------------------------------------
IF MAM_SETUP != 0
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF ; MAM_SETUP
; Setup External Memory Controller ---------------------------------------------
IF (:DEF:NO_EMC_SETUP):LOR:(EMC_SETUP != 0)
LDR R0, =EMC_BASE
LDR R1, =SCB_BASE
LDR R2, =PCB_BASE
LDR R4, [R1, #PCONP_OFS]
ORR R4, R4, #EMC_PCONP_Const ; Enable EMC clock
STR R4, [R1, #PCONP_OFS]
LDR R4, =EMC_CTRL_Val
STR R4, [R0, #EMC_CTRL_OFS]
LDR R4, =EMC_CONFIG_Val
STR R4, [R0, #EMC_CONFIG_OFS]
; Setup pin functions for External Bus functionality
LDR R4, =EMC_PINSEL6_Val
STR R4, [R2, #PINSEL6_OFS]
LDR R4, =EMC_PINSEL8_Val
STR R4, [R2, #PINSEL8_OFS]
LDR R4, =EMC_PINSEL9_Val
STR R4, [R2, #PINSEL9_OFS]
LDR R6, =1200000 ; Number of cycles to delay
Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 48 MHz
BNE Wait_0
IF (EMC_STACS0_SETUP != 0)
LDR R4, =EMC_STA_CFG0_Val
STR R4, [R0, #EMC_STA_CFG0_OFS]
LDR R4, =EMC_STA_WWEN0_Val
STR R4, [R0, #EMC_STA_WWEN0_OFS]
LDR R4, =EMC_STA_WOEN0_Val
STR R4, [R0, #EMC_STA_WOEN0_OFS]
LDR R4, =EMC_STA_WRD0_Val
STR R4, [R0, #EMC_STA_WRD0_OFS]
LDR R4, =EMC_STA_WPAGE0_Val
STR R4, [R0, #EMC_STA_WPAGE0_OFS]
LDR R4, =EMC_STA_WWR0_Val
STR R4, [R0, #EMC_STA_WWR0_OFS]
LDR R4, =EMC_STA_WTURN0_Val
STR R4, [R0, #EMC_STA_WTURN0_OFS]
ENDIF
IF (EMC_STACS1_SETUP != 0)
LDR R4, =EMC_STA_CFG1_Val
STR R4, [R0, #EMC_STA_CFG1_OFS]
LDR R4, =EMC_STA_WWEN1_Val
STR R4, [R0, #EMC_STA_WWEN1_OFS]
LDR R4, =EMC_STA_WOEN1_Val
STR R4, [R0, #EMC_STA_WOEN1_OFS]
LDR R4, =EMC_STA_WRD1_Val
STR R4, [R0, #EMC_STA_WRD1_OFS]
LDR R4, =EMC_STA_WPAGE1_Val
STR R4, [R0, #EMC_STA_WPAGE1_OFS]
LDR R4, =EMC_STA_WWR1_Val
STR R4, [R0, #EMC_STA_WWR1_OFS]
LDR R4, =EMC_STA_WTURN1_Val
STR R4, [R0, #EMC_STA_WTURN1_OFS]
ENDIF
LDR R6, =120000 ; Number of cycles to delay
Wait_1 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 48 MHz
BNE Wait_1
LDR R4, =EMC_STA_EXT_W_Val
LDR R5, =EMC_STA_EXT_W_OFS
ADD R5, R5, R0
STR R4, [R5, #0]
ENDIF ; EMC_SETUP
; Copy Exception Vectors to Internal RAM ---------------------------------------
IF :DEF:RAM_INTVEC
ADR R8, Vectors ; Source
LDR R9, =RAM_BASE ; Destination
LDMIA R8!, {R0-R7} ; Load Vectors
STMIA R9!, {R0-R7} ; Store Vectors
LDMIA R8!, {R0-R7} ; Load Handler Addresses
STMIA R9!, {R0-R7} ; Store Handler Addresses
ENDIF
; Memory Mapping (when Interrupt Vectors are in RAM) ---------------------------
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
IF :DEF:REMAP
LDR R0, =MEMMAP
IF :DEF:EXTMEM_MODE
MOV R1, #3
ELIF :DEF:RAM_MODE
MOV R1, #2
ELSE
MOV R1, #1
ENDIF
STR R1, [R0]
ENDIF
; Setup Stack for each mode ----------------------------------------------------
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IF :DEF:__MICROLIB
EXPORT __initial_sp
ELSE
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
ENDIF
; Enter the C code -------------------------------------------------------------
IMPORT __main
LDR R0, =__main
BX R0
IF :DEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit
ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END
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