/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */#define EBIU_AMGCTL		0xFFC00A00	/* Asynchronous Memory Global Control Register */#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */#define EBIU_SDGCTL		0xFFC00A10	/* SDRAM Global Control Register */#define EBIU_SDBCTL		0xFFC00A14	/* SDRAM Bank Control Register */#define EBIU_SDRRC		0xFFC00A18	/* SDRAM Refresh Rate Control Register */#define EBIU_SDSTAT		0xFFC00A1C	/* SDRAM Status Register *//* DMA Traffic Control Registers */#define DMA_TCPER		0xFFC00B0C	/* Traffic Control Periods Register */#define DMA_TCCNT		0xFFC00B10	/* Traffic Control Current Counts Register *//* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */#define DMA0_NEXT_DESC_PTR	0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */#define DMA0_START_ADDR		0xFFC00C04	/* DMA Channel 0 Start Address Register */#define DMA0_CONFIG		0xFFC00C08	/* DMA Channel 0 Configuration Register */#define DMA0_X_COUNT		0xFFC00C10	/* DMA Channel 0 X Count Register */#define DMA0_X_MODIFY		0xFFC00C14	/* DMA Channel 0 X Modify Register */#define DMA0_Y_COUNT		0xFFC00C18	/* DMA Channel 0 Y Count Register */#define DMA0_Y_MODIFY		0xFFC00C1C	/* DMA Channel 0 Y Modify Register */#define DMA0_CURR_DESC_PTR	0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */#define DMA0_CURR_ADDR		0xFFC00C24	/* DMA Channel 0 Current Address Register */#define DMA0_IRQ_STATUS		0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */#define DMA0_PERIPHERAL_MAP	0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register */#define DMA0_CURR_X_COUNT	0xFFC00C30	/* DMA Channel 0 Current X Count Register */#define DMA0_CURR_Y_COUNT	0xFFC00C38	/* DMA Channel 0 Current Y Count Register */#define DMA1_NEXT_DESC_PTR	0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */#define DMA1_START_ADDR		0xFFC00C44	/* DMA Channel 1 Start Address Register */#define DMA1_CONFIG		0xFFC00C48	/* DMA Channel 1 Configuration Register */#define DMA1_X_COUNT		0xFFC00C50	/* DMA Channel 1 X Count Register */#define DMA1_X_MODIFY		0xFFC00C54	/* DMA Channel 1 X Modify Register */#define DMA1_Y_COUNT		0xFFC00C58	/* DMA Channel 1 Y Count Register */#define DMA1_Y_MODIFY		0xFFC00C5C	/* DMA Channel 1 Y Modify Register */#define DMA1_CURR_DESC_PTR	0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register */#define DMA1_CURR_ADDR		0xFFC00C64	/* DMA Channel 1 Current Address Register */#define DMA1_IRQ_STATUS		0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register */#define DMA1_PERIPHERAL_MAP	0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register */#define DMA1_CURR_X_COUNT	0xFFC00C70	/* DMA Channel 1 Current X Count Register */#define DMA1_CURR_Y_COUNT	0xFFC00C78	/* DMA Channel 1 Current Y Count Register */#define DMA2_NEXT_DESC_PTR	0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register */#define DMA2_START_ADDR		0xFFC00C84	/* DMA Channel 2 Start Address Register */#define DMA2_CONFIG		0xFFC00C88	/* DMA Channel 2 Configuration Register */#define DMA2_X_COUNT		0xFFC00C90	/* DMA Channel 2 X Count Register */#define DMA2_X_MODIFY		0xFFC00C94	/* DMA Channel 2 X Modify Register */#define DMA2_Y_COUNT		0xFFC00C98	/* DMA Channel 2 Y Count Register */#define DMA2_Y_MODIFY		0xFFC00C9C	/* DMA Channel 2 Y Modify Register */#define DMA2_CURR_DESC_PTR	0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register */#define DMA2_CURR_ADDR		0xFFC00CA4	/* DMA Channel 2 Current Address Register */#define DMA2_IRQ_STATUS		0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register */#define DMA2_PERIPHERAL_MAP	0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register */#define DMA2_CURR_X_COUNT	0xFFC00CB0	/* DMA Channel 2 Current X Count Register */#define DMA2_CURR_Y_COUNT	0xFFC00CB8	/* DMA Channel 2 Current Y Count Register */#define DMA3_NEXT_DESC_PTR	0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register */#define DMA3_START_ADDR		0xFFC00CC4	/* DMA Channel 3 Start Address Register */#define DMA3_CONFIG		0xFFC00CC8	/* DMA Channel 3 Configuration Register */#define DMA3_X_COUNT		0xFFC00CD0	/* DMA Channel 3 X Count Register */#define DMA3_X_MODIFY		0xFFC00CD4	/* DMA Channel 3 X Modify Register */#define DMA3_Y_COUNT		0xFFC00CD8	/* DMA Channel 3 Y Count Register */#define DMA3_Y_MODIFY		0xFFC00CDC	/* DMA Channel 3 Y Modify Register */#define DMA3_CURR_DESC_PTR	0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register */#define DMA3_CURR_ADDR		0xFFC00CE4	/* DMA Channel 3 Current Address Register */#define DMA3_IRQ_STATUS		0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register */#define DMA3_PERIPHERAL_MAP	0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register */#define DMA3_CURR_X_COUNT	0xFFC00CF0	/* DMA Channel 3 Current X Count Register */#define DMA3_CURR_Y_COUNT	0xFFC00CF8	/* DMA Channel 3 Current Y Count Register */#define DMA4_NEXT_DESC_PTR	0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register */#define DMA4_START_ADDR		0xFFC00D04	/* DMA Channel 4 Start Address Register */#define DMA4_CONFIG		0xFFC00D08	/* DMA Channel 4 Configuration Register */#define DMA4_X_COUNT		0xFFC00D10	/* DMA Channel 4 X Count Register */#define DMA4_X_MODIFY		0xFFC00D14	/* DMA Channel 4 X Modify Register */#define DMA4_Y_COUNT		0xFFC00D18	/* DMA Channel 4 Y Count Register */#define DMA4_Y_MODIFY		0xFFC00D1C	/* DMA Channel 4 Y Modify Register */#define DMA4_CURR_DESC_PTR	0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register */#define DMA4_CURR_ADDR		0xFFC00D24	/* DMA Channel 4 Current Address Register */#define DMA4_IRQ_STATUS		0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register */#define DMA4_PERIPHERAL_MAP	0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register */#define DMA4_CURR_X_COUNT	0xFFC00D30	/* DMA Channel 4 Current X Count Register */#define DMA4_CURR_Y_COUNT	0xFFC00D38	/* DMA Channel 4 Current Y Count Register */#define DMA5_NEXT_DESC_PTR	0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register */#define DMA5_START_ADDR		0xFFC00D44	/* DMA Channel 5 Start Address Register */#define DMA5_CONFIG		0xFFC00D48	/* DMA Channel 5 Configuration Register */#define DMA5_X_COUNT		0xFFC00D50	/* DMA Channel 5 X Count Register */#define DMA5_X_MODIFY		0xFFC00D54	/* DMA Channel 5 X Modify Register */#define DMA5_Y_COUNT		0xFFC00D58	/* DMA Channel 5 Y Count Register */#define DMA5_Y_MODIFY		0xFFC00D5C	/* DMA Channel 5 Y Modify Register */#define DMA5_CURR_DESC_PTR	0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register */#define DMA5_CURR_ADDR		0xFFC00D64	/* DMA Channel 5 Current Address Register */#define DMA5_IRQ_STATUS		0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register */#define DMA5_PERIPHERAL_MAP	0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register */#define DMA5_CURR_X_COUNT	0xFFC00D70	/* DMA Channel 5 Current X Count Register */#define DMA5_CURR_Y_COUNT	0xFFC00D78	/* DMA Channel 5 Current Y Count Register */#define DMA6_NEXT_DESC_PTR	0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register */#define DMA6_START_ADDR		0xFFC00D84	/* DMA Channel 6 Start Address Register */#define DMA6_CONFIG		0xFFC00D88	/* DMA Channel 6 Configuration Register */#define DMA6_X_COUNT		0xFFC00D90	/* DMA Channel 6 X Count Register */#define DMA6_X_MODIFY		0xFFC00D94	/* DMA Channel 6 X Modify Register */#define DMA6_Y_COUNT		0xFFC00D98	/* DMA Channel 6 Y Count Register */#define DMA6_Y_MODIFY		0xFFC00D9C	/* DMA Channel 6 Y Modify Register */#define DMA6_CURR_DESC_PTR	0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register */#define DMA6_CURR_ADDR		0xFFC00DA4	/* DMA Channel 6 Current Address Register */#define DMA6_IRQ_STATUS		0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register */#define DMA6_PERIPHERAL_MAP	0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register */#define DMA6_CURR_X_COUNT	0xFFC00DB0	/* DMA Channel 6 Current X Count Register */#define DMA6_CURR_Y_COUNT	0xFFC00DB8	/* DMA Channel 6 Current Y Count Register */#define DMA7_NEXT_DESC_PTR	0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register */#define DMA7_START_ADDR		0xFFC00DC4	/* DMA Channel 7 Start Address Register */#define DMA7_CONFIG		0xFFC00DC8	/* DMA Channel 7 Configuration Register */#define DMA7_X_COUNT		0xFFC00DD0	/* DMA Channel 7 X Count Register */#define DMA7_X_MODIFY		0xFFC00DD4	/* DMA Channel 7 X Modify Register */#define DMA7_Y_COUNT		0xFFC00DD8	/* DMA Channel 7 Y Count Register */#define DMA7_Y_MODIFY		0xFFC00DDC	/* DMA Channel 7 Y Modify Register */#define DMA7_CURR_DESC_PTR	0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register */#define DMA7_CURR_ADDR		0xFFC00DE4	/* DMA Channel 7 Current Address Register */#define DMA7_IRQ_STATUS		0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register */#define DMA7_PERIPHERAL_MAP	0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register */#define DMA7_CURR_X_COUNT	0xFFC00DF0	/* DMA Channel 7 Current X Count Register */#define DMA7_CURR_Y_COUNT	0xFFC00DF8	/* DMA Channel 7 Current Y Count Register */#define DMA8_NEXT_DESC_PTR	0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register */#define DMA8_START_ADDR		0xFFC00E04	/* DMA Channel 8 Start Address Register */#define DMA8_CONFIG		0xFFC00E08	/* DMA Channel 8 Configuration Register */#define DMA8_X_COUNT		0xFFC00E10	/* DMA Channel 8 X Count Register */#define DMA8_X_MODIFY		0xFFC00E14	/* DMA Channel 8 X Modify Register */#define DMA8_Y_COUNT		0xFFC00E18	/* DMA Channel 8 Y Count Register */#define DMA8_Y_MODIFY		0xFFC00E1C	/* DMA Channel 8 Y Modify Register */#define DMA8_CURR_DESC_PTR	0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register */#define DMA8_CURR_ADDR		0xFFC00E24	/* DMA Channel 8 Current Address Register */#define DMA8_IRQ_STATUS		0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register */#define DMA8_PERIPHERAL_MAP	0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register */#define DMA8_CURR_X_COUNT	0xFFC00E30	/* DMA Channel 8 Current X Count Register */#define DMA8_CURR_Y_COUNT	0xFFC00E38	/* DMA Channel 8 Current Y Count Register */#define DMA9_NEXT_DESC_PTR	0xFFC00E40	/* DMA Channel 9 Next Descriptor Pointer Register */#define DMA9_START_ADDR		0xFFC00E44	/* DMA Channel 9 Start Address Register */#define DMA9_CONFIG		0xFFC00E48	/* DMA Channel 9 Configuration Register */#define DMA9_X_COUNT		0xFFC00E50	/* DMA Channel 9 X Count Register */#define DMA9_X_MODIFY		0xFFC00E54	/* DMA Channel 9 X Modify Register */#define DMA9_Y_COUNT		0xFFC00E58	/* DMA Channel 9 Y Count Register */#define DMA9_Y_MODIFY		0xFFC00E5C	/* DMA Channel 9 Y Modify Register */#define DMA9_CURR_DESC_PTR	0xFFC00E60	/* DMA Channel 9 Current Descriptor Pointer Register */#define DMA9_CURR_ADDR		0xFFC00E64	/* DMA Channel 9 Current Address Register */#define DMA9_IRQ_STATUS		0xFFC00E68	/* DMA Channel 9 Interrupt/Status Register */#define DMA9_PERIPHERAL_MAP	0xFFC00E6C	/* DMA Channel 9 Peripheral Map Register */#define DMA9_CURR_X_COUNT	0xFFC00E70	/* DMA Channel 9 Current X Count Register */#define DMA9_CURR_Y_COUNT	0xFFC00E78	/* DMA Channel 9 Current Y Count Register */#define DMA10_NEXT_DESC_PTR	0xFFC00E80	/* DMA Channel 10 Next Descriptor Pointer Register */#define DMA10_START_ADDR	0xFFC00E84	/* DMA Channel 10 Start Address Register */#define DMA10_CONFIG		0xFFC00E88	/* DMA Channel 10 Configuration Register */#define DMA10_X_COUNT		0xFFC00E90	/* DMA Channel 10 X Count Register */#define DMA10_X_MODIFY		0xFFC00E94	/* DMA Channel 10 X Modify Register */#define DMA10_Y_COUNT		0xFFC00E98	/* DMA Channel 10 Y Count Register */#define DMA10_Y_MODIFY		0xFFC00E9C	/* DMA Channel 10 Y Modify Register */#define DMA10_CURR_DESC_PTR	0xFFC00EA0	/* DMA Channel 10 Current Descriptor Pointer Register */#define DMA10_CURR_ADDR		0xFFC00EA4	/* DMA Channel 10 Current Address Register */#define DMA10_IRQ_STATUS	0xFFC00EA8	/* DMA Channel 10 Interrupt/Status Register */#define DMA10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA Channel 10 Peripheral Map Register */#define DMA10_CURR_X_COUNT	0xFFC00EB0	/* DMA Channel 10 Current X Count Register */#define DMA10_CURR_Y_COUNT	0xFFC00EB8	/* DMA Channel 10 Current Y Count Register */#define DMA11_NEXT_DESC_PTR	0xFFC00EC0	/* DMA Channel 11 Next Descriptor Pointer Register */#define DMA11_START_ADDR	0xFFC00EC4	/* DMA Channel 11 Start Address Register */#define DMA11_CONFIG		0xFFC00EC8	/* DMA Channel 11 Configuration Register */#define DMA11_X_COUNT		0xFFC00ED0	/* DMA Channel 11 X Count Register */#define DMA11_X_MODIFY		0xFFC00ED4	/* DMA Channel 11 X Modify Register */#define DMA11_Y_COUNT		0xFFC00ED8	/* DMA Channel 11 Y Count Register */#define DMA11_Y_MODIFY		0xFFC00EDC	/* DMA Channel 11 Y Modify Register */#define DMA11_CURR_DESC_PTR	0xFFC00EE0	/* DMA Channel 11 Current Descriptor Pointer Register */#define DMA11_CURR_ADDR		0xFFC00EE4	/* DMA Channel 11 Current Address Register */#define DMA11_IRQ_STATUS	0xFFC00EE8	/* DMA Channel 11 Interrupt/Status Register */#define DMA11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA Channel 11 Peripheral Map Register */#define DMA11_CURR_X_COUNT	0xFFC00EF0	/* DMA Channel 11 Current X Count Register */#define DMA11_CURR_Y_COUNT	0xFFC00EF8	/* DMA Channel 11 Current Y Count Register */#define MDMA_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register */#define MDMA_D0_START_ADDR	0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register */#define MDMA_D0_CONFIG		0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register */#define MDMA_D0_X_COUNT		0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register */#define MDMA_D0_X_MODIFY	0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register */#define MDMA_D0_Y_COUNT		0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register */#define MDMA_D0_Y_MODIFY	0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register */#define MDMA_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register */#define MDMA_D0_CURR_ADDR	0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register */#define MDMA_D0_IRQ_STATUS	0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register */#define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register */#define MDMA_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register */#define MDMA_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register */#define MDMA_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register */