/* * Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved. * *********************************************************************************** * * This include file contains a list of macro "defines" to enable the programmer * to use symbolic names for register-access and bit-manipulation. * *   ---------------------------- *   revision 0.1 *   date: 2004/03/01 21:23:01;  author: joeb *   Initial revision * *   ---------------------------- *   revision 0.2 *   date: 2004/05/15 16:30:00;  author: joeb *   comments: removed I2C/IIC references, changed GPIO sections * *   ---------------------------- *   revision 0.3 *   date: 2004/06/08 12:25:00;  author: joeb *   comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed *             FLAG references in GPIO register names * *   ---------------------------- *   revision 0.4 *   date: 2004/06/09 2:25:00;  author: joeb *   comments: fixed bit-defines for EMAC section, renamed EMAC count registers, *             combined 2 Timer status registers into one * *   ---------------------------- *   revision 0.5 *   date: 2004/08/10 10:25:00;  author: joeb *   comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers * *   ---------------------------- *   revision 0.6 *   date: 2004/08/17 16:25:00;  author: joeb *   comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK * *   ---------------------------- *   revision 0.7 *   date: 2004/08/18 13:21:00;  author: joeb *   comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes * *   ---------------------------- *   revision 0.8 *   date: 2004/08/20 10:24:00;  author: joeb *   comments: Renamed External DMA to Handshake MDMA * *   ---------------------------- *   revision 0.9 *   date: 2004/08/23 13:42:00;  author: joeb *   comments: Renamed Handshake DMA Register Set * *   ---------------------------- *   revision 0.10 *   date: 2004/09/07 11:21:00;  author: joeb *   comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names) * *   ---------------------------- *   revision 0.11 *   date: 2004/09/28 15:14:00;  author: joeb *   comments: Fixed CAN Mailbox Area * *   ---------------------------- *   revision 0.12 *   date: 2004/10/27 13:18:00;  author: joeb *   comments: Added IEEE EMAC Register Support * *   ---------------------------- *   revision 0.13 *   date: 2004/10/28 15:40:00;  author: joeb *   comments: Shortened EMAC Count Register Names * *   ---------------------------- *   revision 0.14 *   date: 2004/11/09 10:45:00;  author: joeb *   comments: Fixed WDSIZE macros * *   ---------------------------- *   revision 0.15 *   date: 2004/11/18 07:45:00;  author: joeb *   comments: Fixed TIMER_STATUS register, added EMAC macros * *   ---------------------------- *   revision 0.16 *   date: 2004/12/13 11:05:00;  author: joeb *   comments: Removed HI/LO macros (now Assembler mnemonics) *				Renamed enable bit for HMDMA from EN to HMDMAEN * *   ---------------------------- *   revision 0.17 *   date: 2004/12/17 14:25:00;  author: joeb *   comments: Replaced C++ Single-Line Comments w/C-standard Comments *				Changed EMAC EQ1024 TX/RX References to GE1024 * *   ---------------------------- *   revision 0.18 *   date: 2005/01/05 10:50:00;  author: joeb *   comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks *				Added mask values for field deposit protection * *   ---------------------------- *   revision 0.19 *   date: 2005/01/10 10:30:00;  author: joeb *   comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10. * *   ---------------------------- *   revision 0.20 *   date: 2005/01/27 14:25:15;  author: joeb *   comments: Moved MMRs common to BF534 to BF534 header. */#ifndef _DEF_BF537_H#define _DEF_BF537_H/* Include all Core registers and bit definitions */#include <asm/arch-common/def_LPBlackfin.h>/* Include all MMR and bit defines common to BF534 */#include <asm/arch-bf537/defBF534.h>/* * Define EMAC Section Unique to BF536/BF537 *//* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */#define	EMAC_OPMODE		0xFFC03000	/* Operating Mode Register */#define EMAC_ADDRLO		0xFFC03004	/* Address Low (32 LSBs) Register */#define EMAC_ADDRHI		0xFFC03008	/* Address High (16 MSBs) Register */#define EMAC_HASHLO		0xFFC0300C	/* Multicast Hash Table Low (Bins 31-0) Register */#define EMAC_HASHHI		0xFFC03010	/* Multicast Hash Table High (Bins 63-32) Register */#define EMAC_STAADD		0xFFC03014	/* Station Management Address Register */#define EMAC_STADAT		0xFFC03018	/* Station Management Data Register */#define EMAC_FLC		0xFFC0301C	/* Flow Control Register */#define EMAC_VLAN1		0xFFC03020	/* VLAN1 Tag Register */#define EMAC_VLAN2		0xFFC03024	/* VLAN2 Tag Register */#define EMAC_WKUP_CTL		0xFFC0302C	/* Wake-Up Control/Status Register */#define EMAC_WKUP_FFMSK0	0xFFC03030	/* Wake-Up Frame Filter 0 Byte Mask Register */#define EMAC_WKUP_FFMSK1	0xFFC03034	/* Wake-Up Frame Filter 1 Byte Mask Register */#define EMAC_WKUP_FFMSK2	0xFFC03038	/* Wake-Up Frame Filter 2 Byte Mask Register */#define EMAC_WKUP_FFMSK3	0xFFC0303C	/* Wake-Up Frame Filter 3 Byte Mask Register */#define EMAC_WKUP_FFCMD		0xFFC03040	/* Wake-Up Frame Filter Commands Register */#define EMAC_WKUP_FFOFF		0xFFC03044	/* Wake-Up Frame Filter Offsets Register */#define EMAC_WKUP_FFCRC0	0xFFC03048	/* Wake-Up Frame Filter 0,1 CRC-16 Register */#define EMAC_WKUP_FFCRC1	0xFFC0304C	/* Wake-Up Frame Filter 2,3 CRC-16 Register */#define	EMAC_SYSCTL		0xFFC03060	/* EMAC System Control Register */#define EMAC_SYSTAT		0xFFC03064	/* EMAC System Status Register */#define EMAC_RX_STAT		0xFFC03068	/* RX Current Frame Status Register */#define EMAC_RX_STKY		0xFFC0306C	/* RX Sticky Frame Status Register */#define EMAC_RX_IRQE		0xFFC03070	/* RX Frame Status Interrupt Enables Register */#define EMAC_TX_STAT		0xFFC03074	/* TX Current Frame Status Register */#define EMAC_TX_STKY		0xFFC03078	/* TX Sticky Frame Status Register */#define EMAC_TX_IRQE		0xFFC0307C	/* TX Frame Status Interrupt Enables Register */#define EMAC_MMC_CTL		0xFFC03080	/* MMC Counter Control Register */#define EMAC_MMC_RIRQS		0xFFC03084	/* MMC RX Interrupt Status Register */#define EMAC_MMC_RIRQE		0xFFC03088	/* MMC RX Interrupt Enables Register */#define EMAC_MMC_TIRQS		0xFFC0308C	/* MMC TX Interrupt Status Register */#define EMAC_MMC_TIRQE		0xFFC03090	/* MMC TX Interrupt Enables Register */#define EMAC_RXC_OK		0xFFC03100	/* RX Frame Successful Count */#define EMAC_RXC_FCS		0xFFC03104	/* RX Frame FCS Failure Count */#define EMAC_RXC_ALIGN		0xFFC03108	/* RX Alignment Error Count */#define EMAC_RXC_OCTET		0xFFC0310C	/* RX Octets Successfully Received Count */#define EMAC_RXC_DMAOVF		0xFFC03110	/* Internal MAC Sublayer Error RX Frame Count */#define EMAC_RXC_UNICST		0xFFC03114	/* Unicast RX Frame Count */#define EMAC_RXC_MULTI		0xFFC03118	/* Multicast RX Frame Count */#define EMAC_RXC_BROAD		0xFFC0311C	/* Broadcast RX Frame Count */#define EMAC_RXC_LNERRI		0xFFC03120	/* RX Frame In Range Error Count */#define EMAC_RXC_LNERRO		0xFFC03124	/* RX Frame Out Of Range Error Count */#define EMAC_RXC_LONG		0xFFC03128	/* RX Frame Too Long Count */#define EMAC_RXC_MACCTL		0xFFC0312C	/* MAC Control RX Frame Count */#define EMAC_RXC_OPCODE		0xFFC03130	/* Unsupported Op-Code RX Frame Count */#define EMAC_RXC_PAUSE		0xFFC03134	/* MAC Control Pause RX Frame Count */#define EMAC_RXC_ALLFRM		0xFFC03138	/* Overall RX Frame Count */#define EMAC_RXC_ALLOCT		0xFFC0313C	/* Overall RX Octet Count */#define EMAC_RXC_TYPED		0xFFC03140	/* Type/Length Consistent RX Frame Count */#define EMAC_RXC_SHORT		0xFFC03144	/* RX Frame Fragment Count - Byte Count x < 64 */#define EMAC_RXC_EQ64		0xFFC03148	/* Good RX Frame Count - Byte Count x = 64 */#define EMAC_RXC_LT128		0xFFC0314C	/* Good RX Frame Count - Byte Count  64 <= x < 128 */#define EMAC_RXC_LT256		0xFFC03150	/* Good RX Frame Count - Byte Count 128 <= x < 256 */#define EMAC_RXC_LT512		0xFFC03154	/* Good RX Frame Count - Byte Count 256 <= x < 512 */#define EMAC_RXC_LT1024		0xFFC03158	/* Good RX Frame Count - Byte Count 512 <= x < 1024 */#define EMAC_RXC_GE1024		0xFFC0315C	/* Good RX Frame Count - Byte Count x >= 1024 */#define EMAC_TXC_OK		0xFFC03180	/* TX Frame Successful Count */#define EMAC_TXC_1COL		0xFFC03184	/* TX Frames Successful After Single Collision Count */#define EMAC_TXC_GT1COL		0xFFC03188	/* TX Frames Successful After Multiple Collisions Count */#define EMAC_TXC_OCTET		0xFFC0318C	/* TX Octets Successfully Received Count */#define EMAC_TXC_DEFER		0xFFC03190	/* TX Frame Delayed Due To Busy Count */#define EMAC_TXC_LATECL		0xFFC03194	/* Late TX Collisions Count */#define EMAC_TXC_XS_COL		0xFFC03198	/* TX Frame Failed Due To Excessive Collisions Count */#define EMAC_TXC_DMAUND		0xFFC0319C	/* Internal MAC Sublayer Error TX Frame Count */#define EMAC_TXC_CRSERR		0xFFC031A0	/* Carrier Sense Deasserted During TX Frame Count */#define EMAC_TXC_UNICST		0xFFC031A4	/* Unicast TX Frame Count */#define EMAC_TXC_MULTI		0xFFC031A8	/* Multicast TX Frame Count */#define EMAC_TXC_BROAD		0xFFC031AC	/* Broadcast TX Frame Count */#define EMAC_TXC_XS_DFR		0xFFC031B0	/* TX Frames With Excessive Deferral Count */#define EMAC_TXC_MACCTL		0xFFC031B4	/* MAC Control TX Frame Count */#define EMAC_TXC_ALLFRM		0xFFC031B8	/* Overall TX Frame Count */#define EMAC_TXC_ALLOCT		0xFFC031BC	/* Overall TX Octet Count */#define EMAC_TXC_EQ64		0xFFC031C0	/* Good TX Frame Count - Byte Count x = 64 */#define EMAC_TXC_LT128		0xFFC031C4	/* Good TX Frame Count - Byte Count  64 <= x < 128 */#define EMAC_TXC_LT256		0xFFC031C8	/* Good TX Frame Count - Byte Count 128 <= x < 256 */#define EMAC_TXC_LT512		0xFFC031CC	/* Good TX Frame Count - Byte Count 256 <= x < 512 */#define EMAC_TXC_LT1024		0xFFC031D0	/* Good TX Frame Count - Byte Count 512 <= x < 1024 */#define EMAC_TXC_GE1024		0xFFC031D4	/* Good TX Frame Count - Byte Count x >= 1024 */#define EMAC_TXC_ABORT		0xFFC031D8	/* Total TX Frames Aborted Count *//* Listing for IEEE-Supported Count Registers */#define FramesReceivedOK		EMAC_RXC_OK	/* RX Frame Successful Count */#define FrameCheckSequenceErrors	EMAC_RXC_FCS	/* RX Frame FCS Failure Count */#define AlignmentErrors			EMAC_RXC_ALIGN	/* RX Alignment Error Count */#define OctetsReceivedOK		EMAC_RXC_OCTET	/* RX Octets Successfully Received Count */#define FramesLostDueToIntMACRcvError	EMAC_RXC_DMAOVF	/* Internal MAC Sublayer Error RX Frame Count */#define UnicastFramesReceivedOK		EMAC_RXC_UNICST	/* Unicast RX Frame Count */#define MulticastFramesReceivedOK	EMAC_RXC_MULTI	/* Multicast RX Frame Count */#define BroadcastFramesReceivedOK	EMAC_RXC_BROAD	/* Broadcast RX Frame Count */#define InRangeLengthErrors		EMAC_RXC_LNERRI	/* RX Frame In Range Error Count */#define OutOfRangeLengthField		EMAC_RXC_LNERRO	/* RX Frame Out Of Range Error Count */#define FrameTooLongErrors		EMAC_RXC_LONG	/* RX Frame Too Long Count */#define MACControlFramesReceived	EMAC_RXC_MACCTL	/* MAC Control RX Frame Count */#define UnsupportedOpcodesReceived	EMAC_RXC_OPCODE	/* Unsupported Op-Code RX Frame Count */#define PAUSEMACCtrlFramesReceived	EMAC_RXC_PAUSE	/* MAC Control Pause RX Frame Count */#define FramesReceivedAll		EMAC_RXC_ALLFRM	/* Overall RX Frame Count */#define OctetsReceivedAll		EMAC_RXC_ALLOCT	/* Overall RX Octet Count */#define TypedFramesReceived		EMAC_RXC_TYPED	/* Type/Length Consistent RX Frame Count */#define FramesLenLt64Received		EMAC_RXC_SHORT	/* RX Frame Fragment Count - Byte Count x < 64 */#define FramesLenEq64Received		EMAC_RXC_EQ64	/* Good RX Frame Count - Byte Count x = 64 */#define FramesLen65_127Received		EMAC_RXC_LT128	/* Good RX Frame Count - Byte Count  64 <= x < 128 */#define FramesLen128_255Received	EMAC_RXC_LT256	/* Good RX Frame Count - Byte Count 128 <= x < 256 */#define FramesLen256_511Received	EMAC_RXC_LT512	/* Good RX Frame Count - Byte Count 256 <= x < 512 */#define FramesLen512_1023Received	EMAC_RXC_LT1024	/* Good RX Frame Count - Byte Count 512 <= x < 1024 */#define FramesLen1024_MaxReceived	EMAC_RXC_GE1024	/* Good RX Frame Count - Byte Count x >= 1024 */#define FramesTransmittedOK		EMAC_TXC_OK	/* TX Frame Successful Count */#define SingleCollisionFrames		EMAC_TXC_1COL	/* TX Frames Successful After Single Collision Count */#define MultipleCollisionFrames		EMAC_TXC_GT1COL	/* TX Frames Successful After Multiple Collisions Count */#define OctetsTransmittedOK		EMAC_TXC_OCTET	/* TX Octets Successfully Received Count */#define FramesWithDeferredXmissions	EMAC_TXC_DEFER	/* TX Frame Delayed Due To Busy Count */#define LateCollisions			EMAC_TXC_LATECL	/* Late TX Collisions Count */#define FramesAbortedDueToXSColls	EMAC_TXC_XS_COL	/* TX Frame Failed Due To Excessive Collisions Count */#define FramesLostDueToIntMacXmitError	EMAC_TXC_DMAUND	/* Internal MAC Sublayer Error TX Frame Count */