break;   /* abort download */	    }	    /* increment target (word)address in NPE memory */	    npeMemAddress++;   	}    }/* condition: block size will fit in NPE memory */    if (status == IX_SUCCESS)    {	if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)	{	    ixNpeDlNpeMgrStats.instructionBlocksLoaded++;	}	else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)	{	    ixNpeDlNpeMgrStats.dataBlocksLoaded++;	}    }    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,		     "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status);    return status;}/* * Function definition: ixNpeDlNpeMgrStateInfoLoad */PRIVATE IX_STATUSixNpeDlNpeMgrStateInfoLoad (    UINT32 npeBaseAddress,    IxNpeDlNpeMgrStateInfoBlock *blockPtr,    BOOL verify){    UINT32 blockSize;    UINT32 ctxtRegAddrInfo;     UINT32 ctxtRegVal;    IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */    UINT32 ctxtNum;            /* identifies Context number (0-16)   */    UINT32 i;    IX_STATUS status = IX_SUCCESS;    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,		     "Entering ixNpeDlNpeMgrStateInfoLoad\n");    /* block size contains number of words of state-info in block */    blockSize = blockPtr->size;        ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);    /* for each state-info context register entry in block */    for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++)    {	/* each state-info entry is 2 words (address, value) in length */	ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo;	ctxtRegVal      = (blockPtr->ctxtRegEntry[i]).value;		ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);	ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >> 	    IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;		/* error-check Context Register No. and Context Number values  */	/* NOTE that there is no STEVT register for Context 0 */	if ((ctxtReg < 0) ||	    (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) ||	    (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) ||	    ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))	{	    IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "				   "invalid Context Register Address\n");	    status = IX_NPEDL_CRITICAL_MICROCODE_ERR;	    ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;	    break;   /* abort download */	}    		status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg,					    ctxtRegVal, verify);	if (status != IX_SUCCESS)	{	    IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "				   "write of state-info to NPE failed\n");	    status = IX_NPEDL_CRITICAL_NPE_ERR;	    ixNpeDlNpeMgrStats.criticalNpeErrors++;	    break;   /* abort download */	}    }/* loop: for each context reg entry in State Info block */        ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);    if (status == IX_SUCCESS)    {	ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++;    }    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,		     "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n",		     status);    return status;}/* * Function definition: ixNpeDlNpeMgrNpeReset */IX_STATUSixNpeDlNpeMgrNpeReset (    IxNpeDlNpeId npeId){    UINT32 npeBaseAddress;    IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */    UINT32 ctxtNum;            /* identifies Context number (0-16)   */    UINT32 regAddr;    UINT32 regVal;    UINT32 localIndex;    UINT32 indexMax;    IX_STATUS status = IX_SUCCESS;    IxFeatureCtrlReg unitFuseReg;    UINT32 ixNpeConfigCtrlRegVal;        IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 		     "Entering ixNpeDlNpeMgrNpeReset\n");        /* get base memory address of NPE from npeId */    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);    /* pre-store the NPE Config Control Register Value */    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal);        ixNpeConfigCtrlRegVal |= 0x3F000000;        /* disable the parity interrupt */    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));        ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);    /*     * clear the FIFOs     */    while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,				      IX_NPEDL_REG_OFFSET_WFIFO,				      IX_NPEDL_MASK_WFIFO_VALID))    {	/* read from the Watch-point FIFO until empty */	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO,			   &regVal);    }        while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,					  IX_NPEDL_REG_OFFSET_STAT,				      IX_NPEDL_MASK_STAT_OFNE))    {	/* read from the outFIFO until empty */	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO,			   &regVal);    }        while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,				      IX_NPEDL_REG_OFFSET_STAT,				      IX_NPEDL_MASK_STAT_IFNE))    {	/*	 * step execution of the NPE intruction to read inFIFO using	 * the Debug Executing Context stack	 */	status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,					   IX_NPEDL_INSTR_RD_FIFO, 0, 0);    if (IX_SUCCESS != status)    {        return status;       }        }        /*     * Reset the mailbox reg     */    /* ...from XScale side */    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST,			IX_NPEDL_REG_RESET_MBST);    /* ...from NPE side */    status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,				       IX_NPEDL_INSTR_RESET_MBOX, 0, 0);    if (IX_SUCCESS != status)    {        return status;       }    /*      *   Reset the physical registers in the NPE register file:     *   Note: no need to save/restore REGMAP for Context 0 here     *   since all Context Store regs are reset in subsequent code     */    for (regAddr = 0;	 (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL);	 regAddr++)    {	/* for each physical register in the NPE reg file, write 0 : */	status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,						0, TRUE);	if (status != IX_SUCCESS)	{	    return status;  /* abort reset */	}    }        /*     * Reset the context store:     */    for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN;	 ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++)    {		/* set each context's Context Store registers to reset values: */	for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++)	{	    /* NOTE that there is no STEVT register for Context 0 */	    if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))	    { 		regVal = ixNpeDlCtxtRegResetValues[ctxtReg];		status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,						    ctxtReg, regVal, TRUE);		if (status != IX_SUCCESS)		{		    return status;  /* abort reset */		}	    }	}    }    ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);    /* write Reset values to Execution Context Stack registers */    indexMax = sizeof (ixNpeDlEcsRegResetValues) /	sizeof (IxNpeDlEcsRegResetValue);    for (localIndex = 0; localIndex < indexMax; localIndex++)    {	regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr;	regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal;	ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal);    }        /* clear the profile counter */    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, 			       IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);        /* clear registers EXCT, AP0, AP1, AP2 and AP3 */    for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;	     regAddr <= IX_NPEDL_REG_OFFSET_AP3;	 regAddr += IX_NPEDL_BYTES_PER_WORD)    {	IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0);    }        /* Reset the Watch-count register */    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0);        /*     * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation     */    /*     * Call the feature control API to fused out and reset the NPE and its     * coprocessor - to reset internal states and remove parity error     */    unitFuseReg = ixFeatureCtrlRead ();    unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId);    ixFeatureCtrlWrite (unitFuseReg);    /* call the feature control API to un-fused and un-reset the NPE & COP */    unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId));    ixFeatureCtrlWrite (unitFuseReg);    /*     * Call NpeMgr function to stop the NPE again after the Feature Control     * has unfused and Un-Reset the NPE and its associated Coprocessors     */    status = ixNpeDlNpeMgrNpeStop (npeId);    /* restore NPE configuration bus Control Register - Parity Settings  */    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL,         (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));    ixNpeDlNpeMgrStats.npeResets++;    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,		     "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status);    return status;}/* * Function definition: ixNpeDlNpeMgrNpeStart */IX_STATUSixNpeDlNpeMgrNpeStart (    IxNpeDlNpeId npeId){    UINT32    npeBaseAddress;    UINT32    ecsRegVal;    BOOL      npeRunning;    IX_STATUS status = IX_SUCCESS;    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 		     "Entering ixNpeDlNpeMgrNpeStart\n");    /* get base memory address of NPE from npeId */    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);    /*     * ensure only Background Context Stack Level is Active by turning off     * the Active bit in each of the other Executing Context Stack levels     */    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,					     IX_NPEDL_ECS_PRI_1_CTXT_REG_0);    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0,				  ecsRegVal);    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,					     IX_NPEDL_ECS_PRI_2_CTXT_REG_0);    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0,				  ecsRegVal);    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,					     IX_NPEDL_ECS_DBG_CTXT_REG_0);    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,				  ecsRegVal);        /* clear the pipeline */    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);        /* start NPE execution by issuing command through EXCTL register on NPE */    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START);    /*     * check execution status of NPE to verify NPE Start operation was     * successful     */    npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,					    IX_NPEDL_REG_OFFSET_EXCTL,					    IX_NPEDL_EXCTL_STATUS_RUN);    if (npeRunning)    {	ixNpeDlNpeMgrStats.npeStarts++;    }    else    {	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: "			       "failed to start NPE execution\n");	status = IX_FAIL;    }        IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,		     "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status);    return status;}/* * Function definition: ixNpeDlNpeMgrNpeStop */IX_STATUSixNpeDlNpeMgrNpeStop (    IxNpeDlNpeId npeId){    UINT32    npeBaseAddress;    IX_STATUS status = IX_SUCCESS;        IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,		     "Entering ixNpeDlNpeMgrNpeStop\n");        /* get base memory address of NPE from npeId */    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);    /* stop NPE execution by issuing command through EXCTL register on NPE */    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP);    /* verify that NPE Stop was successful */    if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,				     IX_NPEDL_EXCTL_STATUS_STOP))    {	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: "			       "failed to stop NPE execution\n");	status = IX_FAIL;    }    ixNpeDlNpeMgrStats.npeStops++;        IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,		     "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status);    return status;}/* * Function definition: ixNpeDlNpeMgrBitsSetCheck */PRIVATE BOOLixNpeDlNpeMgrBitsSetCheck (    UINT32 npeBaseAddress,    UINT32 regOffset,    UINT32 expectedBitsSet){    UINT32 regVal;    IX_NPEDL_REG_READ (npeBaseAddress, regOffset, &regVal);    return expectedBitsSet == (expectedBitsSet & regVal);}/* * Function definition: ixNpeDlNpeMgrStatsShow */voidixNpeDlNpeMgrStatsShow (void){    ixOsalLog (IX_OSAL_LOG_LVL_USER,               IX_OSAL_LOG_DEV_STDOUT,               "\nixNpeDlNpeMgrStatsShow:\n"               "\tInstruction Blocks loaded: %u\n"               "\tData Blocks loaded: %u\n"               "\tState Information Blocks loaded: %u\n"               "\tCritical NPE errors: %u\n"               "\tCritical Microcode errors: %u\n",               ixNpeDlNpeMgrStats.instructionBlocksLoaded,               ixNpeDlNpeMgrStats.dataBlocksLoaded,               ixNpeDlNpeMgrStats.stateInfoBlocksLoaded,               ixNpeDlNpeMgrStats.criticalNpeErrors,               ixNpeDlNpeMgrStats.criticalMicrocodeErrors,               0);    ixOsalLog (IX_OSAL_LOG_LVL_USER,               IX_OSAL_LOG_DEV_STDOUT,               "\tSuccessful NPE Starts: %u\n"               "\tSuccessful NPE Stops: %u\n"               "\tSuccessful NPE Resets: %u\n\n",               ixNpeDlNpeMgrStats.npeStarts,               ixNpeDlNpeMgrStats.npeStops,               ixNpeDlNpeMgrStats.npeResets,               0,0,0);    ixNpeDlNpeMgrUtilsStatsShow ();}/* * Function definition: ixNpeDlNpeMgrStatsReset */voidixNpeDlNpeMgrStatsReset (void){    ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0;    ixNpeDlNpeMgrStats.dataBlocksLoaded = 0;    ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0;    ixNpeDlNpeMgrStats.criticalNpeErrors = 0;    ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0;    ixNpeDlNpeMgrStats.npeStarts = 0;    ixNpeDlNpeMgrStats.npeStops = 0;    ixNpeDlNpeMgrStats.npeResets = 0;    ixNpeDlNpeMgrUtilsStatsReset ();}