/** * @file    IxQMgrAqmIf_p.h * * @author Intel Corporation * @date    30-Oct-2001 * * @brief   The IxQMgrAqmIf sub-component provides a number of inline * functions for performing I/O on the AQM.  * * Because  some functions contained in this module are inline and are * used in other modules (within the QMgr component) the definitions are * contained in this header file. The "normal" use of inline functions * is to use the inline functions in the module in which they are * defined. In this case these inline functions are used in external * modules and therefore the use of "inline extern". What this means * is as follows: if a function foo is declared as "inline extern"this * definition is only used for inlining, in no case is the function * compiled on its own. If the compiler cannot inline the function it * becomes an external reference. Therefore in IxQMgrAqmIf.c all * inline functions are defined without the "inline extern" specifier * and so define the external references. In all other modules these * funtions are defined as "inline extern". * *  * @par * IXP400 SW Release version 2.0 *  * -- Copyright Notice -- *  * @par * Copyright 2001-2005, Intel Corporation. * All rights reserved. *  * @par * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. Neither the name of the Intel Corporation nor the names of its contributors *    may be used to endorse or promote products derived from this software *    without specific prior written permission. *  * @par * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. *  * @par * -- End of Copyright Notice --*/#ifndef IXQMGRAQMIF_P_H#define IXQMGRAQMIF_P_H#include "IxOsalTypes.h"/* * inline definition */ #ifdef IX_OSAL_INLINE_ALL/* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as   inline functions */#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN#else   #ifdef IXQMGRAQMIF_C#ifndef IX_QMGR_AQMIF_INLINE#define IX_QMGR_AQMIF_INLINE#endif#else  #ifndef IX_QMGR_AQMIF_INLINE#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN#endif#endif /* IXQMGRAQMIF_C */#endif /* IX_OSAL_INLINE *//* * User defined include files. */#include "IxQMgr.h"#include "IxQMgrLog_p.h"#include "IxQMgrQCfg_p.h"/* Because this file contains inline functions which will be compiled into * other components, we need to ensure that the IX_COMPONENT_NAME define * is set to ix_qmgr while this code is being compiled.  This will ensure * that the correct implementation is provided for the memory access macros * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file. * This must be done before including "IxOsalMemAccess.h" */#define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME#undef  IX_COMPONENT_NAME#define IX_COMPONENT_NAME ix_qmgr#include "IxOsal.h" /* * #defines and macros used in this file. *//* Number of bytes per word */#define IX_QMGR_NUM_BYTES_PER_WORD 4/* Underflow bit mask  */#define IX_QMGR_UNDERFLOW_BIT_OFFSET    0x0/* Overflow bit mask */#define IX_QMGR_OVERFLOW_BIT_OFFSET     0x1/* Queue access register, queue 0 */#define IX_QMGR_QUEACC0_OFFSET      0x0000/* Size of queue access register in words */#define IX_QMGR_QUEACC_SIZE         0x4/*words*//* Queue status register, queues 0-7 */#define IX_QMGR_QUELOWSTAT0_OFFSET  (IX_QMGR_QUEACC0_OFFSET +\(IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))/* Queue status register, queues 8-15 */#define IX_QMGR_QUELOWSTAT1_OFFSET  (IX_QMGR_QUELOWSTAT0_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Queue status register, queues 16-23 */#define IX_QMGR_QUELOWSTAT2_OFFSET  (IX_QMGR_QUELOWSTAT1_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Queue status register, queues 24-31 */#define IX_QMGR_QUELOWSTAT3_OFFSET  (IX_QMGR_QUELOWSTAT2_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Queue status register Q status bits mask */#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF/* Size of queue 0-31 status register */#define IX_QMGR_QUELOWSTAT_SIZE     0x4 /*words*//* The number of queues' status specified per word */#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8/* Queue UF/OF status register queues 0-15  */#define IX_QMGR_QUEUOSTAT0_OFFSET   (IX_QMGR_QUELOWSTAT3_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Queue UF/OF status register queues 16-31 */#define IX_QMGR_QUEUOSTAT1_OFFSET   (IX_QMGR_QUEUOSTAT0_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* The number of queues' underflow/overflow status specified per word */#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10/* Queue NE status register, queues 32-63   */#define IX_QMGR_QUEUPPSTAT0_OFFSET  (IX_QMGR_QUEUOSTAT1_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Queue F status register, queues 32-63    */#define IX_QMGR_QUEUPPSTAT1_OFFSET  (IX_QMGR_QUEUPPSTAT0_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Size of queue 32-63 status register */#define IX_QMGR_QUEUPPSTAT_SIZE     0x2 /*words*//* The number of queues' status specified per word */#define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20/* Queue INT source select register, queues 0-7   */#define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET   +\                                       IX_QMGR_NUM_BYTES_PER_WORD)/* Queue INT source select register, queues 8-15  */#define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\                                       IX_QMGR_NUM_BYTES_PER_WORD)/* Queue INT source select register, queues 16-23 */#define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\                                       IX_QMGR_NUM_BYTES_PER_WORD)/* Queue INT source select register, queues 24-31 */#define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\                                       IX_QMGR_NUM_BYTES_PER_WORD)/* Size of interrupt source select reegister */#define IX_QMGR_INT0SRCSELREG_SIZE  0x4 /*words*//* The number of queues' interrupt source select specified per word*/#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8/* Queue INT enable register, queues 0-31  */#define IX_QMGR_QUEIEREG0_OFFSET    (IX_QMGR_INT0SRCSELREG3_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Queue INT enable register, queues 32-63 */#define IX_QMGR_QUEIEREG1_OFFSET    (IX_QMGR_QUEIEREG0_OFFSET      +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Queue INT register, queues 0-31  */#define IX_QMGR_QINTREG0_OFFSET     (IX_QMGR_QUEIEREG1_OFFSET +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Queue INT register, queues 32-63 */#define IX_QMGR_QINTREG1_OFFSET     (IX_QMGR_QINTREG0_OFFSET  +\                                     IX_QMGR_NUM_BYTES_PER_WORD)/* Size of interrupt register */#define IX_QMGR_QINTREG_SIZE        0x2 /*words*//* Number of queues' status specified per word */#define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20/* Number of bits per queue interrupt status */#define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1#define IX_QMGR_QINTREG_BIT_OFFSET 0x1/* Size of address space not used by AQM */#define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES  0x1bC0/* Queue config register, queue 0 */#define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\                             IX_QMGR_NUM_BYTES_PER_WORD +\                             IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)/* Total size of configuration words */#define IX_QMGR_QUECONFIG_SIZE      0x100/* Start of SRAM queue buffer space */#define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\                                 IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)/* Total bits in a word */#define BITS_PER_WORD 32/* Size of queue buffer space */#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00/* * This macro will return the address of the access register for the * queue  specified by qId */#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\        (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\	 + IX_QMGR_QUEACC0_OFFSET)/*  * Bit location of bit-3 of INT0SRCSELREG0 register to enabled * sticky interrupt register. */#define IX_QMGR_INT0SRCSELREG0_BIT3 3/* * Variable declerations global to this file. Externs are followed by * statics. */extern UINT32 aqmBaseAddress;/* * Function declarations. */voidixQMgrAqmIfInit (void);voidixQMgrAqmIfUninit (void);unsignedixQMgrAqmIfLog2 (unsigned number);voidixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, 			       UINT32 registerBaseAddrOffset,			       unsigned queuesPerRegWord,			       UINT32 value);voidixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,				 IxQMgrSourceId srcSel,				 unsigned int *statusWordOffset,				 UINT32 *checkValue,				 UINT32 *mask);/* * The Xscale software allways deals with logical addresses and so the * base address of the AQM memory space is not a hardcoded value. This * function must be called before any other function in this component. * NO CHECKING is performed to ensure that the base address has been * set. */voidixQMgrAqmIfBaseAddressSet (UINT32 address);/* * Get the base address of the AQM memory space. */voidixQMgrAqmIfBaseAddressGet (UINT32 *address);/* * Get the sram base address */voidixQMgrAqmIfSramBaseAddressGet (UINT32 *address);/* * Read a queue status */voidixQMgrAqmIfQueStatRead (IxQMgrQId qId,			IxQMgrQStatus* status);/* *   Set INT0SRCSELREG0 Bit3  */ void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);/* * Set the interrupt source */voidixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,			   IxQMgrSourceId sourceId);/* * Enable interruptson a queue */voidixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);/* * Disable interrupt on a quee */voidixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);/* * Write the config register of the specified queue */voidixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,			IxQMgrQSizeInWords qSizeInWords,			IxQMgrQEntrySizeInWords entrySizeInWords,			UINT32 freeSRAMAddress);/* * read fields from the config of the specified queue. */voidixQMgrAqmIfQueCfgRead (IxQMgrQId qId,		       unsigned int numEntries,		       UINT32 *baseAddress,		       unsigned int *ne,		       unsigned int *nf,		       UINT32 *readPtr,		       UINT32 *writePtr);/* * Set the ne and nf watermark level on a queue. */voidixQMgrAqmIfWatermarkSet (IxQMgrQId qId,			 unsigned ne,			 unsigned nf);/* Inspect an entry without moving the read pointer */IX_STATUSixQMgrAqmIfQPeek (IxQMgrQId qId,		  unsigned int entryIndex,		  unsigned int *entry);/* Modify an entry without moving the write pointer */IX_STATUSixQMgrAqmIfQPoke (IxQMgrQId qId,		  unsigned int entryIndex,		  unsigned int *entry);/* * Function prototype for inline functions. For description refers to  * the functions defintion below. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfWordWrite (VUINT32 *address,		      UINT32 word);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfWordRead (VUINT32 *address,		     UINT32 *word);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQPop (IxQMgrQId qId,		 IxQMgrQEntrySizeInWords numWords,		 UINT32 *entry);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQPush (IxQMgrQId qId,		  IxQMgrQEntrySizeInWords numWords,		  UINT32 *entry);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, 			    UINT32 *qStatusWords);IX_QMGR_AQMIF_INLINE BOOLixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,			 UINT32 *newQStatusWords,			 unsigned int statusWordOffset,			 			 UINT32 checkValue,			 UINT32 mask);IX_QMGR_AQMIF_INLINE BOOLixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, 			     UINT32 registerBaseAddrOffset,			     unsigned queuesPerRegWord,			     unsigned relativeBitOffset,			     BOOL reset);IX_QMGR_AQMIF_INLINE BOOLixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);IX_QMGR_AQMIF_INLINE BOOLixQMgrAqmIfOverflowCheck (IxQMgrQId qId);IX_QMGR_AQMIF_INLINE UINT32ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, 			      UINT32 registerBaseAddrOffset,			      unsigned queuesPerRegWord);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, 			       UINT32 reg);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, 			      UINT32 *regVal);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,			   IxQMgrQStatus *status);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,			   IxQMgrQStatus *status);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQueStatRead (IxQMgrQId qId, 			IxQMgrQStatus *qStatus);IX_QMGR_AQMIF_INLINE unsignedixQMgrAqmIfPow2NumDivide (unsigned numerator, 			  unsigned denominator);IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, 			            UINT32 *regVal);/* * Inline functions */