/* * This inline function is used by other QMgr components to write one * word to the specified address. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfWordWrite (VUINT32 *address,		      UINT32 word){    IX_OSAL_WRITE_LONG(address, word);}/* * This inline function is used by other QMgr components to read a * word from the specified address. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfWordRead (VUINT32 *address,		     UINT32 *word){    *word = IX_OSAL_READ_LONG(address);}/* * This inline function is used by other QMgr components to pop an * entry off the specified queue. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQPop (IxQMgrQId qId,		 IxQMgrQEntrySizeInWords numWords,		 UINT32 *entry){    volatile UINT32 *accRegAddr;    accRegAddr = (UINT32*)(aqmBaseAddress +    			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));    switch (numWords)    {	case IX_QMGR_Q_ENTRY_SIZE1:	    ixQMgrAqmIfWordRead (accRegAddr, entry);	    break;	case IX_QMGR_Q_ENTRY_SIZE2:	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);	    ixQMgrAqmIfWordRead (accRegAddr, entry);	    break;	case IX_QMGR_Q_ENTRY_SIZE4:	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);	    ixQMgrAqmIfWordRead (accRegAddr, entry);	    break;	default:	    IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");	    break;    }}/* * This inline function is used by other QMgr components to push an * entry to the specified queue. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQPush (IxQMgrQId qId,		  IxQMgrQEntrySizeInWords numWords,		  UINT32 *entry){    volatile UINT32 *accRegAddr;    accRegAddr = (UINT32*)(aqmBaseAddress +    			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));        switch (numWords)    {	case IX_QMGR_Q_ENTRY_SIZE1:	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);	    break;	case IX_QMGR_Q_ENTRY_SIZE2:	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);	    break;	case IX_QMGR_Q_ENTRY_SIZE4:	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);	    break;	default:	    IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");	    break;    }}/* * The AQM interrupt registers contains a bit for each AQM queue * specifying the queue (s) that cause an interrupt to fire. This * function is called by IxQMGrDispatcher component. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, 			    UINT32 *qStatusWords){    volatile UINT32 *regAddress = NULL;    if (group == IX_QMGR_QUELOW_GROUP)    {	regAddress = (UINT32*)(aqmBaseAddress +			       IX_QMGR_QUELOWSTAT0_OFFSET);	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);	ixQMgrAqmIfWordRead (regAddress, qStatusWords);    }    else /* We have the upper queues */    {       /* Only need to read the Nearly Empty status register for	* queues 32-63 as for therse queues the interrtupt source	* condition is fixed to Nearly Empty	*/	regAddress = (UINT32*)(aqmBaseAddress +			       IX_QMGR_QUEUPPSTAT0_OFFSET);	ixQMgrAqmIfWordRead (regAddress, qStatusWords);    }}/* * This function check if the status for a queue has changed between * 2 snapshots and if it has, that the status matches a particular * value after masking. */IX_QMGR_AQMIF_INLINE BOOLixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,			 UINT32 *newQStatusWords,			 unsigned int statusWordOffset,			 			 UINT32 checkValue,			 UINT32 mask){    if (((oldQStatusWords[statusWordOffset] & mask) != 	 (newQStatusWords[statusWordOffset] & mask)) &&	((newQStatusWords[statusWordOffset] & mask) == checkValue))    {	return TRUE;    }    return FALSE;}/* * The AQM interrupt register contains a bit for each AQM queue * specifying the queue (s) that cause an interrupt to fire. This * function is called by IxQMgrDispatcher component. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, 			      UINT32 *regVal){    volatile UINT32 *regAddress;    if (group == IX_QMGR_QUELOW_GROUP)    {	regAddress = (UINT32*)(aqmBaseAddress +			       IX_QMGR_QINTREG0_OFFSET);    }    else    {	regAddress = (UINT32*)(aqmBaseAddress +			       IX_QMGR_QINTREG1_OFFSET);    }    ixQMgrAqmIfWordRead (regAddress, regVal);}/* * The AQM interrupt enable register contains a bit for each AQM queue. * This function reads the interrupt enable register. This * function is called by IxQMgrDispatcher component. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, 			            UINT32 *regVal){    volatile UINT32 *regAddress;    if (group == IX_QMGR_QUELOW_GROUP)    {	regAddress = (UINT32*)(aqmBaseAddress +			       IX_QMGR_QUEIEREG0_OFFSET);    }    else    {	regAddress = (UINT32*)(aqmBaseAddress +			       IX_QMGR_QUEIEREG1_OFFSET);    }    ixQMgrAqmIfWordRead (regAddress, regVal);}/* * This inline function will read the status bit of a queue * specified by qId. If reset is TRUE the bit is cleared. */IX_QMGR_AQMIF_INLINE BOOLixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, 			     UINT32 registerBaseAddrOffset,			     unsigned queuesPerRegWord,			     unsigned relativeBitOffset,			     BOOL reset){    UINT32 actualBitOffset;    volatile UINT32 *registerAddress;    UINT32 registerWord;    /*     * Calculate the registerAddress     * multiple queues split accross registers     */    registerAddress = (UINT32*)(aqmBaseAddress +    				registerBaseAddrOffset +    				((qId / queuesPerRegWord) *    				 IX_QMGR_NUM_BYTES_PER_WORD));    /*     * Get the status word     */    ixQMgrAqmIfWordRead (registerAddress, &registerWord);        /*     * Calculate the actualBitOffset     * status for multiple queues stored in one register     */    actualBitOffset = (relativeBitOffset + 1) <<	((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));    /* Check if the status bit is set */    if (registerWord & actualBitOffset)    {	/* Clear the bit if reset */	if (reset)	{	    ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));	}	return TRUE;    }    /* Bit not set */    return FALSE;}/* * @ingroup IxQmgrAqmIfAPI * * @brief Read the underflow status of a queue  * * This inline function will read the underflow status of a queue * specified by qId. *  */IX_QMGR_AQMIF_INLINE BOOLixQMgrAqmIfUnderflowCheck (IxQMgrQId qId){    if (qId < IX_QMGR_MIN_QUEUPP_QID)    {	return (ixQMgrAqmIfRegisterBitCheck (qId,					     IX_QMGR_QUEUOSTAT0_OFFSET,					     IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,					     IX_QMGR_UNDERFLOW_BIT_OFFSET,					     TRUE/*reset*/));    }    else    {	/* Qs 32-63 have no underflow status */	return FALSE;    }}/* * This inline function will read the overflow status of a queue * specified by qId. */IX_QMGR_AQMIF_INLINE BOOLixQMgrAqmIfOverflowCheck (IxQMgrQId qId){    if (qId < IX_QMGR_MIN_QUEUPP_QID)    {	return (ixQMgrAqmIfRegisterBitCheck (qId,					     IX_QMGR_QUEUOSTAT0_OFFSET,					     IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,					     IX_QMGR_OVERFLOW_BIT_OFFSET,					     TRUE/*reset*/));    }    else    {	/* Qs 32-63 have no overflow status */	return FALSE;    }}/* * This inline function will read the status bits of a queue * specified by qId. */IX_QMGR_AQMIF_INLINE UINT32ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, 			      UINT32 registerBaseAddrOffset,			      unsigned queuesPerRegWord){    volatile UINT32 *registerAddress;    UINT32 registerWord;    UINT32 statusBitsMask;    UINT32 bitsPerQueue;    bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;    /*     * Calculate the registerAddress     * multiple queues split accross registers     */    registerAddress = (UINT32*)(aqmBaseAddress +				registerBaseAddrOffset +				((qId / queuesPerRegWord) *				 IX_QMGR_NUM_BYTES_PER_WORD));    /*     * Read the status word     */    ixQMgrAqmIfWordRead (registerAddress, &registerWord);        /*     * Calculate the mask for the status bits for this queue.     */    statusBitsMask = ((1 << bitsPerQueue) - 1);    /*     * Shift the status word so it is right justified     */        registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);    /*     * Mask out all bar the status bits for this queue     */    return (registerWord &= statusBitsMask);}/* * This function is called by IxQMgrDispatcher to set the contents of * the AQM interrupt register. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, 			       UINT32 reg){    volatile UINT32 *address;    if (group == IX_QMGR_QUELOW_GROUP)    {	address = (UINT32*)(aqmBaseAddress +			    IX_QMGR_QINTREG0_OFFSET);    }    else    {	address = (UINT32*)(aqmBaseAddress +			    IX_QMGR_QINTREG1_OFFSET);    }    ixQMgrAqmIfWordWrite (address, reg);}/* * Read the status of a queue in the range 0-31. * * This function is used by other QMgr components to read the * status of the queue specified by qId. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,			   IxQMgrQStatus *status){    /* Read the general status bits */    *status = ixQMgrAqmIfQRegisterBitsRead (qId,					    IX_QMGR_QUELOWSTAT0_OFFSET,					    IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);}/* * This function will read the status of the queue specified * by qId. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,			   IxQMgrQStatus *status){    /* Reset the status bits */    *status = 0;    /*      * Check if the queue is nearly empty,     * N.b. QUPP stat register contains status for regs 32-63 at each     *      bit position so subtract 32 to get bit offset     */    if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),				     IX_QMGR_QUEUPPSTAT0_OFFSET,				     IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,				     0/*relativeBitOffset*/,				     FALSE/*!reset*/))    {	*status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;    }    /*      * Check if the queue is full,     * N.b. QUPP stat register contains status for regs 32-63 at each     *      bit position so subtract 32 to get bit offset     */    if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),				     IX_QMGR_QUEUPPSTAT1_OFFSET,				     IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,				     0/*relativeBitOffset*/,				     FALSE/*!reset*/))    {	*status |= IX_QMGR_Q_STATUS_F_BIT_MASK;    }}/* * This function is used by other QMgr components to read the * status of the queue specified by qId. */IX_QMGR_AQMIF_INLINE voidixQMgrAqmIfQueStatRead (IxQMgrQId qId, 			IxQMgrQStatus *qStatus){    if (qId < IX_QMGR_MIN_QUEUPP_QID)    {	ixQMgrAqmIfQueLowStatRead (qId, qStatus);    }    else    {	ixQMgrAqmIfQueUppStatRead (qId, qStatus);    }}/* * This function performs a mod division */IX_QMGR_AQMIF_INLINE unsignedixQMgrAqmIfPow2NumDivide (unsigned numerator, 			  unsigned denominator){    /* Number is evenly divisable by 2 */    return (numerator >> ixQMgrAqmIfLog2 (denominator));}/* Restore IX_COMPONENT_NAME */#undef IX_COMPONENT_NAME#define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME#endif/*IXQMGRAQMIF_P_H*/