*/#define IX_NPE_A_QMQ_HSS0_PKT_TX2       IX_QMGR_QUEUE_16/** * @def IX_NPE_A_QMQ_HSS0_PKT_TX3 * * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3 */#define IX_NPE_A_QMQ_HSS0_PKT_TX3       IX_QMGR_QUEUE_17/** * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0 * * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0 */#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0  IX_QMGR_QUEUE_18/** * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1 * * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1 */#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1  IX_QMGR_QUEUE_19/** * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2 * * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2 */#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2  IX_QMGR_QUEUE_20/** * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3 * * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3 */#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3  IX_QMGR_QUEUE_21/** * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE * * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue */#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE   IX_QMGR_QUEUE_22/****  HSS Port 1 ****//** * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG * * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger */#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG   IX_QMGR_QUEUE_10/** * @def IX_NPE_A_QMQ_HSS1_PKT_RX * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive */#define IX_NPE_A_QMQ_HSS1_PKT_RX        IX_QMGR_QUEUE_0/** * @def IX_NPE_A_QMQ_HSS1_PKT_TX0 * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0 */#define IX_NPE_A_QMQ_HSS1_PKT_TX0       IX_QMGR_QUEUE_5/** * @def IX_NPE_A_QMQ_HSS1_PKT_TX1 * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1 */#define IX_NPE_A_QMQ_HSS1_PKT_TX1       IX_QMGR_QUEUE_6/** * @def IX_NPE_A_QMQ_HSS1_PKT_TX2 * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2 */#define IX_NPE_A_QMQ_HSS1_PKT_TX2       IX_QMGR_QUEUE_7/** * @def IX_NPE_A_QMQ_HSS1_PKT_TX3 * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3 */#define IX_NPE_A_QMQ_HSS1_PKT_TX3       IX_QMGR_QUEUE_8/** * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0 * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0 */#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0  IX_QMGR_QUEUE_1/** * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1 * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1 */#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1  IX_QMGR_QUEUE_2/** * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2 * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2 */#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2  IX_QMGR_QUEUE_3/** * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3 * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3 */#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3  IX_QMGR_QUEUE_4/** * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE * * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue */#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE   IX_QMGR_QUEUE_9/***************************************************************************************** * Queue assignments for DMA *****************************************************************************************/#define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19   /**< Queue Id for NPE A DMA Request */#define IX_DMA_NPE_A_DONE_QID    IX_QMGR_QUEUE_20   /**< Queue Id for NPE A DMA Done    */#define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24   /**< Queue Id for NPE B DMA Request */#define IX_DMA_NPE_B_DONE_QID    IX_QMGR_QUEUE_26   /**< Queue Id for NPE B DMA Done    */#define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25   /**< Queue Id for NPE C DMA Request */#define IX_DMA_NPE_C_DONE_QID    IX_QMGR_QUEUE_27   /**< Queue Id for NPE C DMA Done    *//***************************************************************************************** * Queue assignments for Ethernet * * Note: Rx queue definitions, which include QoS traffic class definitions * are managed by EthDB and declared in IxEthDBQoS.h *****************************************************************************************//**** @def IX_ETH_ACC_RX_FRAME_ETH_Q ** @brief  Eth0/Eth1 NPE Frame Recieve Q.** @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration* */#define IX_ETH_ACC_RX_FRAME_ETH_Q 	(IX_QMGR_QUEUE_4)/**** @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q** @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1**/#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q    (IX_QMGR_QUEUE_27)/**** @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q** @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2**/#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q    (IX_QMGR_QUEUE_28)/**** @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q** @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3**/#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q    (IX_QMGR_QUEUE_26)/**** @def IX_ETH_ACC_TX_FRAME_ENET0_Q** @brief Submit frame Q for NPEB Eth 0 - Port 1**/#define IX_ETH_ACC_TX_FRAME_ENET0_Q    (IX_QMGR_QUEUE_24)/**** @def IX_ETH_ACC_TX_FRAME_ENET1_Q** @brief Submit frame Q for NPEC Eth 1 - Port 2**/#define IX_ETH_ACC_TX_FRAME_ENET1_Q    (IX_QMGR_QUEUE_25)/**** @def IX_ETH_ACC_TX_FRAME_ENET2_Q** @brief Submit frame Q for NPEA Eth 2 - Port 3**/#define IX_ETH_ACC_TX_FRAME_ENET2_Q    (IX_QMGR_QUEUE_23)/**** @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q** @brief Transmit complete Q for NPE Eth 0/1, Port 1&2**/#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q    (IX_QMGR_QUEUE_31)/***************************************************************************************** * Queue assignments for Crypto *****************************************************************************************//** Crypto Service Request Queue */#define IX_CRYPTO_ACC_CRYPTO_REQ_Q  (IX_QMGR_QUEUE_29)/** Crypto Service Done Queue */#define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)/** Crypto Req Q CB tag */#define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG   (0)/** Crypto Done Q CB tag */#define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG  (1)/** WEP Service Request Queue */#define IX_CRYPTO_ACC_WEP_REQ_Q  (IX_QMGR_QUEUE_21)/** WEP Service Done Queue */#define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)/** WEP Req Q CB tag */#define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG      (2)/** WEP Done Q CB tag */#define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG     (3)/** Number of queues allocate to crypto hardware accelerator services */#define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q       (2)/** Number of queues allocate to WEP NPE services */#define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q      (2)                                                      /** Number of queues allocate to CryptoAcc component */#define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)   #endif /* IxQueueAssignments_H */