/* *  Copyright (c) 2005 *  Travis B. Sawyer,  Sandburst Corporation, tsawyer@sandburst.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <config.h>#include <common.h>#include <command.h>#include "metrobox.h"#include "metrobox_version.h"#include <asm/processor.h>#include <asm/io.h>#include <spd_sdram.h>#include <i2c.h>#include "../common/ppc440gx_i2c.h"#include "../common/sb_common.h"void fpga_init (void);METROBOX_BOARD_ID_ST board_id_as[] ={	{"Undefined"},			    /* Not specified */	{"2x10Gb"},			    /* 2 ports, 10 GbE */	{"20x1Gb"},			    /* 20 ports, 1 GbE */	{"Reserved"},			     /* Reserved for future use */};/************************************************************************* *  board_early_init_f * *  Setup chip selects, initialize the Opto-FPGA, initialize *  interrupt polarity and triggers. ************************************************************************/int board_early_init_f (void){	ppc440_gpio_regs_t *gpio_regs;	/* Enable GPIO interrupts */	mtsdr(sdr_pfc0, 0x00103E00);	/* Setup access for LEDs, and system topology info */	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;	/* Turn on all the leds for now */	gpio_regs->out = SBCOMMON_GPIO_LEDS;	/*--------------------------------------------------------------------+	  | Initialize EBC CONFIG	  +-------------------------------------------------------------------*/	mtebc(xbcfg,	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |	      EBC_CFG_PR_32);	/*--------------------------------------------------------------------+	  | 1/2 MB FLASH. Initialize bank 0 with default values.	  +-------------------------------------------------------------------*/	mtebc(pb0ap,	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |	      EBC_BXAP_PEN_DISABLED);	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);	/*--------------------------------------------------------------------+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.	  +-------------------------------------------------------------------*/	mtebc(pb1ap,	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |	      EBC_BXAP_PEN_DISABLED);	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);	/*--------------------------------------------------------------------+	  | Compact Flash, uses 2 Chip Selects (2 & 6)	  +-------------------------------------------------------------------*/	mtebc(pb2ap,	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |	      EBC_BXAP_PEN_DISABLED);	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);	/*--------------------------------------------------------------------+	  | OPTO & OFEM FPGA. Initialize bank 3 with default values.	  +-------------------------------------------------------------------*/	mtebc(pb3ap,	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);	/*--------------------------------------------------------------------+	  | MAC A for metrobox	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses	  | Initialize bank 4 with default values.	  +-------------------------------------------------------------------*/	mtebc(pb4ap,	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);	mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);	/*--------------------------------------------------------------------+	  | Metrobox MAC B  Initialize bank 5 with default values.	  | KA REF FPGA	 Initialize bank 5 with default values.	  +-------------------------------------------------------------------*/	mtebc(pb5ap,	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);	mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);	/*--------------------------------------------------------------------+	  | Compact Flash, uses 2 Chip Selects (2 & 6)	  +-------------------------------------------------------------------*/	mtebc(pb6ap,	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |	      EBC_BXAP_PEN_DISABLED);	mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);	/*--------------------------------------------------------------------+	  | BME-32. Initialize bank 7 with default values.	  +-------------------------------------------------------------------*/	mtebc(pb7ap,	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);	/*--------------------------------------------------------------------+	 * Setup the interrupt controller polarities, triggers, etc.	 +-------------------------------------------------------------------*/	mtdcr (uic0sr, 0xffffffff);	/* clear all */	mtdcr (uic0er, 0x00000000);	/* disable all */	mtdcr (uic0cr, 0x00000000);	/* all non- critical */	mtdcr (uic0pr, 0xfffffe03);	/* polarity */	mtdcr (uic0tr, 0x01c00000);	/* trigger edge vs level */	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */	mtdcr (uic0sr, 0xffffffff);	/* clear all */	mtdcr (uic1sr, 0xffffffff);	/* clear all */	mtdcr (uic1er, 0x00000000);	/* disable all */	mtdcr (uic1cr, 0x00000000);	/* all non-critical */	mtdcr (uic1pr, 0xffffc8ff);	/* polarity */	mtdcr (uic1tr, 0x00ff0000);	/* trigger edge vs level */	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */	mtdcr (uic1sr, 0xffffffff);	/* clear all */	mtdcr (uic2sr, 0xffffffff);	/* clear all */	mtdcr (uic2er, 0x00000000);	/* disable all */	mtdcr (uic2cr, 0x00000000);	/* all non-critical */	mtdcr (uic2pr, 0xffff83ff);	/* polarity */	mtdcr (uic2tr, 0x00ff8c0f);	/* trigger edge vs level */	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */	mtdcr (uic2sr, 0xffffffff);	/* clear all */	mtdcr (uicb0sr, 0xfc000000);	/* clear all */	mtdcr (uicb0er, 0x00000000);	/* disable all */	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */	mtdcr (uicb0pr, 0xfc000000);	mtdcr (uicb0tr, 0x00000000);	mtdcr (uicb0vr, 0x00000001);	fpga_init();	return 0;}/************************************************************************* *  checkboard * *  Dump pertinent info to the console ************************************************************************/int checkboard (void){	sys_info_t sysinfo;	unsigned char brd_rev, brd_id;	unsigned short sernum;	unsigned char opto_rev, opto_id;	OPTO_FPGA_REGS_ST *opto_ps;	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;	opto_rev = (unsigned char)((opto_ps->revision_ul &				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);	opto_id = (unsigned char)((opto_ps->revision_ul &				   SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)				  >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);	brd_rev = (unsigned char)((opto_ps->boardinfo_ul &				   SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)				  >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);	brd_id = (unsigned char)((opto_ps->boardinfo_ul &				  SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)				 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);	get_sys_info (&sysinfo);	sernum = sbcommon_get_serial_number();	printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);	printf ("%s\n", METROBOX_U_BOOT_REL_STR);	printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);	if (sbcommon_get_master()) {		printf("Slot 0 - Master\nSlave board");		if (sbcommon_secondary_present())			printf(" present\n");		else			printf(" not detected\n");	} else {		printf("Slot 1 - Slave\n\n");