/* * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * * Port to AMCC-440SPE Evaluation Board SOP - April 2005 * * PCIe supporting routines derived from Linux 440SPe PCIe driver. */#include <common.h>#include <ppc4xx.h>#include <asm/processor.h>#include <i2c.h>#include <asm-ppc/io.h>#include "yucca.h"#include "../cpu/ppc4xx/440spe_pcie.h"DECLARE_GLOBAL_DATA_PTR;#undef PCIE_ENDPOINT/* #define PCIE_ENDPOINT 1 */void fpga_init (void);void get_sys_info(PPC440_SYS_INFO *board_cfg );int compare_to_true(char *str );char *remove_l_w_space(char *in_str );char *remove_t_w_space(char *in_str );int get_console_port(void);int ppc440spe_init_pcie_rootport(int port);void ppc440spe_setup_pcie(struct pci_controller *hose, int port);#define DEBUG_ENV#ifdef DEBUG_ENV#define DEBUGF(fmt,args...) printf(fmt ,##args)#else#define DEBUGF(fmt,args...)#endif#define FALSE	0#define TRUE	1int board_early_init_f (void){/*----------------------------------------------------------------------------+| Define Boot devices+----------------------------------------------------------------------------*/#define BOOT_FROM_SMALL_FLASH		0x00#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01#define BOOT_FROM_PCI			0x02#define BOOT_DEVICE_UNKNOWN		0x03/*----------------------------------------------------------------------------+| EBC Devices Characteristics|   Peripheral Bank Access Parameters       -   EBC_BxAP|   Peripheral Bank Configuration Register  -   EBC_BxCR+----------------------------------------------------------------------------*//* * Small Flash and FRAM * BU Value * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000 * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000 */#define EBC_BXAP_SMALL_FLASH		EBC_BXAP_BME_DISABLED	| \					EBC_BXAP_TWT_ENCODE(7)	| \					EBC_BXAP_BCE_DISABLE	| \					EBC_BXAP_BCT_2TRANS	| \					EBC_BXAP_CSN_ENCODE(0)	| \					EBC_BXAP_OEN_ENCODE(0)	| \					EBC_BXAP_WBN_ENCODE(0)	| \					EBC_BXAP_WBF_ENCODE(0)	| \					EBC_BXAP_TH_ENCODE(0)	| \					EBC_BXAP_RE_DISABLED	| \					EBC_BXAP_SOR_DELAYED	| \					EBC_BXAP_BEM_WRITEONLY	| \					EBC_BXAP_PEN_DISABLED#define EBC_BXCR_SMALL_FLASH_CS0	EBC_BXCR_BAS_ENCODE(0xFF000000)	| \					EBC_BXCR_BS_16MB		| \					EBC_BXCR_BU_RW			| \					EBC_BXCR_BW_8BIT#define EBC_BXCR_SMALL_FLASH_CS2	EBC_BXCR_BAS_ENCODE(0xe7000000)	| \					EBC_BXCR_BS_16MB		| \					EBC_BXCR_BU_RW			| \					EBC_BXCR_BW_8BIT/* * Large Flash and SRAM * BU Value * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000 * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000*/#define EBC_BXAP_LARGE_FLASH		EBC_BXAP_BME_DISABLED	| \					EBC_BXAP_TWT_ENCODE(7)	| \					EBC_BXAP_BCE_DISABLE	| \					EBC_BXAP_BCT_2TRANS	| \					EBC_BXAP_CSN_ENCODE(0)	| \					EBC_BXAP_OEN_ENCODE(0)	| \					EBC_BXAP_WBN_ENCODE(0)	| \					EBC_BXAP_WBF_ENCODE(0)	| \					EBC_BXAP_TH_ENCODE(0)	| \					EBC_BXAP_RE_DISABLED	| \					EBC_BXAP_SOR_DELAYED	| \					EBC_BXAP_BEM_WRITEONLY	| \					EBC_BXAP_PEN_DISABLED#define EBC_BXCR_LARGE_FLASH_CS0	EBC_BXCR_BAS_ENCODE(0xFF000000)	| \					EBC_BXCR_BS_16MB		| \					EBC_BXCR_BU_RW			| \					EBC_BXCR_BW_16BIT#define EBC_BXCR_LARGE_FLASH_CS2	EBC_BXCR_BAS_ENCODE(0xE7000000)	| \					EBC_BXCR_BS_16MB		| \					EBC_BXCR_BU_RW			| \					EBC_BXCR_BW_16BIT/* * FPGA * BU value : * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000 */#define EBC_BXAP_FPGA			EBC_BXAP_BME_DISABLED	| \					EBC_BXAP_TWT_ENCODE(11)	| \					EBC_BXAP_BCE_DISABLE	| \					EBC_BXAP_BCT_2TRANS	| \					EBC_BXAP_CSN_ENCODE(10)	| \					EBC_BXAP_OEN_ENCODE(1)	| \					EBC_BXAP_WBN_ENCODE(1)	| \					EBC_BXAP_WBF_ENCODE(1)	| \					EBC_BXAP_TH_ENCODE(1)	| \					EBC_BXAP_RE_DISABLED	| \					EBC_BXAP_SOR_DELAYED	| \					EBC_BXAP_BEM_RW		| \					EBC_BXAP_PEN_DISABLED#define EBC_BXCR_FPGA_CS1		EBC_BXCR_BAS_ENCODE(0xe2000000)	| \					EBC_BXCR_BS_1MB			| \					EBC_BXCR_BU_RW			| \					EBC_BXCR_BW_16BIT	 unsigned long mfr;	/*	 * Define Variables for EBC initialization depending on BOOTSTRAP option	 */	unsigned long sdr0_pinstp, sdr0_sdstp1 ;	unsigned long bootstrap_settings, ebc_data_width, boot_selection;	int computed_boot_device = BOOT_DEVICE_UNKNOWN;	/*-------------------------------------------------------------------+	 | Initialize EBC CONFIG -	 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC	 | default value :	 |	0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000	 |	 +-------------------------------------------------------------------*/	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |			EBC_CFG_PTD_ENABLE |			EBC_CFG_RTC_16PERCLK |			EBC_CFG_ATC_PREVIOUS |			EBC_CFG_DTC_PREVIOUS |			EBC_CFG_CTC_PREVIOUS |			EBC_CFG_OEO_PREVIOUS |			EBC_CFG_EMC_DEFAULT |			EBC_CFG_PME_DISABLE |			EBC_CFG_PR_16);	/*-------------------------------------------------------------------+	 |	 |  PART 1 : Initialize EBC Bank 1	 |  ==============================	 | Bank1 is always associated to the EPLD.	 | It has to be initialized prior to other banks settings computation	 | since some board registers values may be needed to determine the	 | boot type	 |	 +-------------------------------------------------------------------*/	mtebc(pb1ap, EBC_BXAP_FPGA);	mtebc(pb1cr, EBC_BXCR_FPGA_CS1);	/*-------------------------------------------------------------------+	 |	 |  PART 2 : Determine which boot device was selected	 |  =================================================	 |	 |  Read Pin Strap Register in PPC440SPe	 |  Result can either be :	 |   - Boot strap = boot from EBC 8bits     => Small Flash	 |   - Boot strap = boot from PCI	 |   - Boot strap = IIC	 |  In case of boot from IIC, read Serial Device Strap Register1	 |	 |  Result can either be :	 |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash	 |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM	 |   - Boot from PCI	 |	 +-------------------------------------------------------------------*/	/* Read Pin Strap Register in PPC440SP */	mfsdr(SDR0_PINSTP, sdr0_pinstp);	bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;	switch (bootstrap_settings) {		case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:			/*			 * Strapping Option A			 * Boot from EBC - 8 bits , Small Flash			 */			computed_boot_device = BOOT_FROM_SMALL_FLASH;			break;		case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:			/*			 * Strappping Option B			 * Boot from PCI			 */			computed_boot_device = BOOT_FROM_PCI;			break;		case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:		case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:			/*			 * Strapping Option C or D			 * Boot Settings in IIC EEprom address 0x50 or 0x54			 * Read Serial Device Strap Register1 in PPC440SPe			 */			mfsdr(SDR0_SDSTP1, sdr0_sdstp1);			boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;			ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;			switch (boot_selection) {				case SDR0_SDSTP1_ERPN_EBC:					switch (ebc_data_width) {						case SDR0_SDSTP1_EBCW_16_BITS:							computed_boot_device =								BOOT_FROM_LARGE_FLASH_OR_SRAM;							break;						case SDR0_SDSTP1_EBCW_8_BITS :							computed_boot_device = BOOT_FROM_SMALL_FLASH;							break;					}					break;				case SDR0_SDSTP1_ERPN_PCI:					computed_boot_device = BOOT_FROM_PCI;					break;				default:					/* should not occure */					computed_boot_device = BOOT_DEVICE_UNKNOWN;			}			break;		default:			/* should not be */			computed_boot_device = BOOT_DEVICE_UNKNOWN;			break;	}	/*-------------------------------------------------------------------+	 |	 |  PART 3 : Compute EBC settings depending on selected boot device	 |  ======   ======================================================	 |	 | Resulting EBC init will be among following configurations :	 |	 |  - Boot from EBC 8bits => boot from Small Flash selected	 |            EBC-CS0     = Small Flash	 |            EBC-CS2     = Large Flash and SRAM	 |	 |  - Boot from EBC 16bits => boot from Large Flash or SRAM	 |            EBC-CS0     = Large Flash or SRAM	 |            EBC-CS2     = Small Flash	 |	 |  - Boot from PCI	 |            EBC-CS0     = not initialized to avoid address contention	 |            EBC-CS2     = same as boot from Small Flash selected	 |	 +-------------------------------------------------------------------*/	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;	switch (computed_boot_device) {		/*-------------------------------------------------------------------*/		case BOOT_FROM_PCI:		/*-------------------------------------------------------------------*/			/*			 * By Default CS2 is affected to LARGE Flash			 * do not initialize SMALL FLASH to avoid address contention			 * Large Flash			 */			ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;			ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;			break;		/*-------------------------------------------------------------------*/		case BOOT_FROM_SMALL_FLASH:		/*-------------------------------------------------------------------*/			ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;			ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;			/*			 * Large Flash or SRAM			 */			/* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */			ebc0_cs2_bxap_value = 0x048ff240;			ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;			break;		/*-------------------------------------------------------------------*/		case BOOT_FROM_LARGE_FLASH_OR_SRAM:		/*-------------------------------------------------------------------*/			ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;			ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;			/* Small flash */			ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;			ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;			break;		/*-------------------------------------------------------------------*/		default:		/*-------------------------------------------------------------------*/			/* BOOT_DEVICE_UNKNOWN */			break;	}	mtebc(pb0ap, ebc0_cs0_bxap_value);