}	l_sect = -1;	/* Disable interrupts which might cause a timeout here */	flag = disable_interrupts();	/* Start erase on unprotected sectors */	for (sect = s_first; sect <= s_last; sect++) {		if (info->protect[sect] == 0) {	/* not protected */			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */				for (i = 0; i < 50; i++)					udelay(1000);	/* wait 1 ms */			} else {				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */			}			l_sect = sect;			/*			 * Wait for each sector to complete, it's more			 * reliable.  According to AMD Spec, you must			 * issue all erase commands within a specified			 * timeout.  This has been seen to fail, especially			 * if printf()s are included (for debug)!!			 */			wait_for_DQ7_1(info, sect);		}	}	/* re-enable interrupts if necessary */	if (flag)		enable_interrupts();	/* wait at least 80us - let's wait 1 ms */	udelay(1000);	/* reset to read mode */	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */	printf(" done\n");	return 0;}/*----------------------------------------------------------------------- * Copy memory to flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt){	ulong cp, wp, data;	int i, l, rc;	wp = (addr & ~3);	/* get lower word aligned address */	/*	 * handle unaligned start bytes	 */	if ((l = addr - wp) != 0) {		data = 0;		for (i = 0, cp = wp; i < l; ++i, ++cp) {			data = (data << 8) | (*(uchar *) cp);		}		for (; i < 4 && cnt > 0; ++i) {			data = (data << 8) | *src++;			--cnt;			++cp;		}		for (; cnt == 0 && i < 4; ++i, ++cp) {			data = (data << 8) | (*(uchar *) cp);		}		if ((rc = write_word(info, wp, data)) != 0) {			return rc;		}		wp += 4;	}	/*	 * handle word aligned part	 */	while (cnt >= 4) {		data = 0;		for (i = 0; i < 4; ++i) {			data = (data << 8) | *src++;		}		if ((rc = write_word(info, wp, data)) != 0) {			return rc;		}		wp += 4;		cnt -= 4;	}	if (cnt == 0) {		return 0;	}	/*	 * handle unaligned tail bytes	 */	data = 0;	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {		data = (data << 8) | *src++;		--cnt;	}	for (; i < 4; ++i, ++cp) {		data = (data << 8) | (*(uchar *) cp);	}	return (write_word(info, wp, data));}/*----------------------------------------------------------------------- * Copy memory to flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */#ifdef FLASH_BASE1_PRELIMstatic int write_word(flash_info_t * info, ulong dest, ulong data){	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {		return write_word_2(info, dest, data);	} else {		return write_word_1(info, dest, data);	}}static int write_word_1(flash_info_t * info, ulong dest, ulong data)#elsestatic int write_word(flash_info_t * info, ulong dest, ulong data)#endif{	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;	ulong start;	int i;	/* Check if Flash is (sufficiently) erased */	if ((*((vu_long *)dest) & data) != data) {		return 2;	}	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {		int flag;		/* Disable interrupts which might cause a timeout here */		flag = disable_interrupts();		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;		dest2[i] = data2[i];		/* re-enable interrupts if necessary */		if (flag)			enable_interrupts();		/* data polling for D7 */		start = get_timer(0);		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {				return 1;			}		}	}	return 0;}#ifdef FLASH_BASE1_PRELIM/* * The following code cannot be run from FLASH! */static ulong flash_get_size_2(vu_long * addr, flash_info_t * info){	short i;	CFG_FLASH_CHAR_SIZE value;	ulong base = (ulong) addr;	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);	/* Write auto select command: read Manufacturer ID */	addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;	addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;	addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;	udelay(1000);	value = (CFG_FLASH_CHAR_SIZE)addr2[0];	DEBUGF("FLASH MANUFACT: %x\n", value);	switch (value) {	case (CFG_FLASH_CHAR_SIZE) AMD_MANUFACT:		info->flash_id = FLASH_MAN_AMD;		break;	case (CFG_FLASH_CHAR_SIZE) FUJ_MANUFACT:		info->flash_id = FLASH_MAN_FUJ;		break;	case (CFG_FLASH_CHAR_SIZE) SST_MANUFACT:		info->flash_id = FLASH_MAN_SST;		break;	case (CFG_FLASH_CHAR_SIZE) STM_MANUFACT:		info->flash_id = FLASH_MAN_STM;		break;	default:		info->flash_id = FLASH_UNKNOWN;		info->sector_count = 0;		info->size = 0;		return 0;		/* no or unknown flash */	}	value = (CFG_FLASH_CHAR_SIZE)addr2[2];	/* device ID */	DEBUGF("\nFLASH DEVICEID: %x\n", value);	switch (value) {	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV040B:		info->flash_id += FLASH_AM040;		info->sector_count = 8;		info->size = 0x0080000;	/* => 512 ko */		break;	case (CFG_FLASH_CHAR_SIZE) AMD_ID_F040B:		info->flash_id += FLASH_AM040;		info->sector_count = 8;		info->size = 0x0080000;	/* => 512 ko */		break;	case (CFG_FLASH_CHAR_SIZE) STM_ID_M29W040B:		info->flash_id += FLASH_AM040;		info->sector_count = 8;		info->size = 0x0080000;	/* => 512 ko */		break;	case (CFG_FLASH_CHAR_SIZE) AMD_ID_F016D:		info->flash_id += FLASH_AMD016;		info->sector_count = 32;		info->size = 0x00200000;		break;			/* => 2 MB */	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV033C:		info->flash_id += FLASH_AMDLV033C;		info->sector_count = 64;		info->size = 0x00400000;		break;			/* => 4 MB */	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400T:		info->flash_id += FLASH_AM400T;		info->sector_count = 11;		info->size = 0x00080000;		break;			/* => 0.5 MB */	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400B:		info->flash_id += FLASH_AM400B;		info->sector_count = 11;		info->size = 0x00080000;		break;			/* => 0.5 MB */	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800T:		info->flash_id += FLASH_AM800T;		info->sector_count = 19;		info->size = 0x00100000;		break;			/* => 1 MB */	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800B:		info->flash_id += FLASH_AM800B;		info->sector_count = 19;		info->size = 0x00100000;		break;			/* => 1 MB */	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160T:		info->flash_id += FLASH_AM160T;		info->sector_count = 35;		info->size = 0x00200000;		break;			/* => 2 MB */	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160B:		info->flash_id += FLASH_AM160B;		info->sector_count = 35;		info->size = 0x00200000;		break;			/* => 2 MB */	case (CFG_FLASH_CHAR_SIZE) AMD_ID_MIRROR:		if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_2				&& (CFG_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) {			info->flash_id += FLASH_AMLV128U;			info->sector_count = 256;			info->size = 0x01000000;		} else if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_2				&& (CFG_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) {			info->flash_id += FLASH_S29GL128N;			info->sector_count = 128;			info->size = 0x01000000;		}		else			info->flash_id = FLASH_UNKNOWN;		break;			/* => 2 MB */	default:		info->flash_id = FLASH_UNKNOWN;		return 0;		/* => no or unknown flash */	}	/* set up sector start address table */	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {		for (i = 0; i < info->sector_count; i++)			info->start[i] = base + (i * 0x00010000);	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {		for (i = 0; i < info->sector_count; i++)			info->start[i] = base + (i * 0x00010000);	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {		for (i = 0; i < info->sector_count; i++)			info->start[i] = base + (i * 0x00020000);	} else {		if (info->flash_id & FLASH_BTYPE) {			/* set sector offsets for bottom boot block type */			info->start[0] = base + 0x00000000;			info->start[1] = base + 0x00004000;			info->start[2] = base + 0x00006000;			info->start[3] = base + 0x00008000;			for (i = 4; i < info->sector_count; i++) {				info->start[i] =				    base + (i * 0x00010000) - 0x00030000;			}		} else {			/* set sector offsets for top boot block type */			i = info->sector_count - 1;			info->start[i--] = base + info->size - 0x00004000;			info->start[i--] = base + info->size - 0x00006000;			info->start[i--] = base + info->size - 0x00008000;			for (; i >= 0; i--) {				info->start[i] = base + i * 0x00010000;			}		}	}	/* check for protected sectors */	for (i = 0; i < info->sector_count; i++) {		/* read sector protection at sector address, (A7 .. A0) = 0x02 */		/* D0 = 1 if protected */		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);		/* For AMD29033C flash we need to resend the command of *		 * reading flash protection for upper 8 Mb of flash     */		if (i == 32) {			addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;			addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;			addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;		}		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)			info->protect[i] = 0;		else			info->protect[i] = (CFG_FLASH_CHAR_SIZE)addr2[4] & 1;	}	/* issue bank reset to return to read mode */	addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0;	return info->size;}static int wait_for_DQ7_2(flash_info_t * info, int sect){	ulong start, now, last;	volatile CFG_FLASH_WORD_SIZE *addr =	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);	start = get_timer(0);	last = start;	while (((CFG_FLASH_WORD_SIZE)addr[0] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=	       (CFG_FLASH_WORD_SIZE) 0x80808080) {		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {			printf("Timeout\n");			return -1;		}		/* show that we're waiting */		if ((now - last) > 1000) { /* every second */			putc('.');			last = now;		}	}	return 0;}static int flash_erase_2(flash_info_t * info, int s_first, int s_last){	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);	volatile CFG_FLASH_WORD_SIZE *addr2;	int flag, prot, sect, l_sect;	int i;	if ((s_first < 0) || (s_first > s_last)) {		if (info->flash_id == FLASH_UNKNOWN) {			printf("- missing\n");		} else {			printf("- no sectors to erase\n");		}		return 1;	}	if (info->flash_id == FLASH_UNKNOWN) {		printf("Can't erase unknown flash type - aborted\n");		return 1;	}	prot = 0;	for (sect = s_first; sect <= s_last; ++sect) {		if (info->protect[sect]) {			prot++;		}	}	if (prot) {		printf("- Warning: %d protected sectors will not be erased!\n",		       prot);	} else {		printf("\n");	}	l_sect = -1;	/* Disable interrupts which might cause a timeout here */	flag = disable_interrupts();	/* Start erase on unprotected sectors */	for (sect = s_first; sect <= s_last; sect++) {		if (info->protect[sect] == 0) {	/* not protected */			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x50505050;	/* block erase */				for (i = 0; i < 50; i++)					udelay(1000);	/* wait 1 ms */			} else {				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30303030;	/* sector erase */			}			l_sect = sect;			/*			 * Wait for each sector to complete, it's more			 * reliable.  According to AMD Spec, you must			 * issue all erase commands within a specified			 * timeout.  This has been seen to fail, especially			 * if printf()s are included (for debug)!!			 */			wait_for_DQ7_2(info, sect);		}	}	/* re-enable interrupts if necessary */	if (flag)		enable_interrupts();	/* wait at least 80us - let's wait 1 ms */	udelay(1000);	/* reset to read mode */	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];	addr[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */	printf(" done\n");	return 0;}static int write_word_2(flash_info_t * info, ulong dest, ulong data){	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;	ulong start;	int i;	/* Check if Flash is (sufficiently) erased */	if ((*((vu_long *)dest) & data) != data) {		return 2;	}	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {		int flag;		/* Disable interrupts which might cause a timeout here */		flag = disable_interrupts();		addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;		addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;		addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA0A0A0A0;		dest2[i] = data2[i];		/* re-enable interrupts if necessary */		if (flag)			enable_interrupts();		/* data polling for D7 */		start = get_timer(0);		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080)) {			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {				return 1;			}		}	}	return 0;}#endif /* FLASH_BASE1_PRELIM */