/* * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <common.h>#include <asm/processor.h>#include <asm/gpio.h>#include <spd_sdram.h>#include <ppc440.h>#include "bamboo.h"void ext_bus_cntlr_init(void);void configure_ppc440ep_pins(void);int is_nand_selected(void);#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))/************************************************************************* * * Bamboo has one bank onboard sdram (plus DIMM) * * Fixed memory is composed of : *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, *	13 row add bits, 10 column add bits (but 12 row used only). *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, *	12 row add bits, 10 column add bits. *	Prepare a subset (only the used ones) of SPD data * *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of *	the corresponding bank is divided by 2 due to number of Row addresses *	12 in the ECC module * *  Assumes:	64 MB, ECC, non-registered *		PLB @ 133 MHz * ************************************************************************/const unsigned char cfg_simulate_spd_eeprom[128] = {	0x80,    /* number of SPD bytes used: 128 */	0x08,    /*  total number bytes in SPD device = 256 */	0x07,    /* DDR ram */#ifdef CONFIG_DDR_ECC	0x0C,    /* num Row Addr: 12 */#else	0x0D,    /* num Row Addr: 13 */#endif	0x09,    /* numColAddr: 9  */	0x01,    /* numBanks: 1 */	0x20,    /* Module data width: 32 bits */	0x00,    /* Module data width continued: +0 */	0x04,    /* 2.5 Volt */	0x75,    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */#ifdef CONFIG_DDR_ECC	0x02,    /* ECC ON : 02 OFF : 00 */#else	0x00,    /* ECC ON : 02 OFF : 00 */#endif	0x82,    /* refresh Rate Type: Normal (15.625us) + Self refresh */	0,	0,	0,	0x01,    /* wcsbc = 1 */	0,	0,	0x0C,    /* casBit (2,2.5) */	0,	0,	0x00,    /* not registered: 0  registered : 0x02*/	0,	0xA0,    /* SDRAM Cycle Time (cas latency 2) = 10 ns */	0,	0x00,    /* SDRAM Cycle Time (cas latency 1.5) = N.A */	0,	0x50,    /* tRpNs = 20 ns  */	0,	0x50,    /* tRcdNs = 20 ns */	45,      /* tRasNs */#ifdef CONFIG_DDR_ECC	0x08,    /* bankSizeID: 32MB */#else	0x10,    /* bankSizeID: 64MB */#endif	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0};#endif#if 0{	   /* GPIO   Alternate1	      Alternate2	Alternate3 */    {	/* GPIO Core 0 */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0	-> EBC_ADDR(7)	    DMA_REQ(2) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1	-> EBC_ADDR(6)	    DMA_ACK(2) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2	-> EBC_ADDR(5)	    DMA_EOT/TC(2) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3	-> EBC_ADDR(4)	    DMA_REQ(3) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4	-> EBC_ADDR(3)	    DMA_ACK(3) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6	-> EBC_CS_N(1) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7	-> EBC_CS_N(2) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8	-> EBC_CS_N(3) */	{ GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9	 -> EBC_CS_N(4) */	{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->		    USB2D_RXVALID */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ	    USB2D_RXERROR */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->		    USB2D_TXVALID */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA	    USB2D_PAD_SUSPNDM */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK	    USB2D_XCVRSELECT */	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */    },    {	/* GPIO Core 1 */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0	-> USB2D_OPMODE0 */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1	-> USB2D_OPMODE1 */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2	-> UART0_DCD_N	    UART1_DSR_CTS_N   UART2_SOUT */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3	-> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4	-> UART0_8PIN_CTS_N		      UART3_SIN */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5	-> UART0_RTS_N */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6	-> UART0_DTR_N	    UART1_SOUT */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7	-> UART0_RI_N	    UART1_SIN */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8	-> UIC_IRQ(0) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9	-> UIC_IRQ(1) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)	    DMA_ACK(1) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)	    DMA_EOT/TC(1) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)	    DMA_REQ(0) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)	    DMA_ACK(0) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)	    DMA_EOT/TC(0) */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \	   Can be unselected thru TraceSelect Bit */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /	      in PowerPC440EP Chip */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */    }};#endif/*----------------------------------------------------------------------------+  | EBC Devices Characteristics  |   Peripheral Bank Access Parameters	      -	  EBC0_BnAP  |   Peripheral Bank Configuration Register  -	  EBC0_BnCR  +----------------------------------------------------------------------------*//* Small Flash */#define EBC0_BNAP_SMALL_FLASH				\	EBC0_BNAP_BME_DISABLED			|	\	EBC0_BNAP_TWT_ENCODE(6)			|	\	EBC0_BNAP_CSN_ENCODE(0)	    		|	\	EBC0_BNAP_OEN_ENCODE(1)	    		|	\	EBC0_BNAP_WBN_ENCODE(1)	    		|	\	EBC0_BNAP_WBF_ENCODE(3)	    		|	\	EBC0_BNAP_TH_ENCODE(1)	    		|	\	EBC0_BNAP_RE_ENABLED	    		|	\	EBC0_BNAP_SOR_DELAYED	    		|	\	EBC0_BNAP_BEM_WRITEONLY	    		|	\	EBC0_BNAP_PEN_DISABLED#define EBC0_BNCR_SMALL_FLASH_CS0			\	EBC0_BNCR_BAS_ENCODE(0xFFF00000)    	| 	\	EBC0_BNCR_BS_1MB		    	|	\	EBC0_BNCR_BU_RW			    	|	\	EBC0_BNCR_BW_8BIT#define EBC0_BNCR_SMALL_FLASH_CS4			\	EBC0_BNCR_BAS_ENCODE(0x87F00000)    	| 	\	EBC0_BNCR_BS_1MB		    	|	\	EBC0_BNCR_BU_RW			    	|	\	EBC0_BNCR_BW_8BIT/* Large Flash or SRAM */#define EBC0_BNAP_LARGE_FLASH_OR_SRAM			\	EBC0_BNAP_BME_DISABLED	    		|	\	EBC0_BNAP_TWT_ENCODE(8)	    		|	\	EBC0_BNAP_CSN_ENCODE(0)	    		|	\	EBC0_BNAP_OEN_ENCODE(1)	    		|	\	EBC0_BNAP_WBN_ENCODE(1)	    		|	\	EBC0_BNAP_WBF_ENCODE(1)	    		|	\	EBC0_BNAP_TH_ENCODE(2)	    		|	\	EBC0_BNAP_SOR_DELAYED	    		|	\	EBC0_BNAP_BEM_RW	    		|	\	EBC0_BNAP_PEN_DISABLED#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0   		\	EBC0_BNCR_BAS_ENCODE(0xFF800000)	| 	\	EBC0_BNCR_BS_8MB		    	|	\	EBC0_BNCR_BU_RW			    	|	\	EBC0_BNCR_BW_16BIT#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4   		\	EBC0_BNCR_BAS_ENCODE(0x87800000)	| 	\	EBC0_BNCR_BS_8MB		    	|	\	EBC0_BNCR_BU_RW			    	|	\	EBC0_BNCR_BW_16BIT/* NVRAM - FPGA */#define EBC0_BNAP_NVRAM_FPGA				\	EBC0_BNAP_BME_DISABLED	    		|	\	EBC0_BNAP_TWT_ENCODE(9)	    		|	\	EBC0_BNAP_CSN_ENCODE(0)	    		|	\	EBC0_BNAP_OEN_ENCODE(1)	    		|	\	EBC0_BNAP_WBN_ENCODE(1)	    		|	\	EBC0_BNAP_WBF_ENCODE(0)	    		|	\	EBC0_BNAP_TH_ENCODE(2)	    		|	\	EBC0_BNAP_RE_ENABLED	    		|	\	EBC0_BNAP_SOR_DELAYED	    		|	\	EBC0_BNAP_BEM_WRITEONLY	    		|	\	EBC0_BNAP_PEN_DISABLED#define EBC0_BNCR_NVRAM_FPGA_CS5			\	EBC0_BNCR_BAS_ENCODE(0x80000000)    	| 	\	EBC0_BNCR_BS_1MB		    	|	\	EBC0_BNCR_BU_RW			    	|	\	EBC0_BNCR_BW_8BIT/* Nand Flash */#define EBC0_BNAP_NAND_FLASH				\	EBC0_BNAP_BME_DISABLED	    		|	\	EBC0_BNAP_TWT_ENCODE(3)	    		|	\	EBC0_BNAP_CSN_ENCODE(0)	    		|	\	EBC0_BNAP_OEN_ENCODE(0)	    		|	\	EBC0_BNAP_WBN_ENCODE(0)	    		|	\	EBC0_BNAP_WBF_ENCODE(0)	    		|	\	EBC0_BNAP_TH_ENCODE(1)	    		|	\	EBC0_BNAP_RE_ENABLED	    		|	\	EBC0_BNAP_SOR_NOT_DELAYED   		|	\	EBC0_BNAP_BEM_RW	    		|	\	EBC0_BNAP_PEN_DISABLED#define EBC0_BNCR_NAND_FLASH_CS0	0xB8400000/* NAND0 */#define EBC0_BNCR_NAND_FLASH_CS1			\	EBC0_BNCR_BAS_ENCODE(0x90000000)    	| 	\	EBC0_BNCR_BS_1MB		    	|	\	EBC0_BNCR_BU_RW			    	|	\	EBC0_BNCR_BW_32BIT/* NAND1 - Bank2 */#define EBC0_BNCR_NAND_FLASH_CS2			\	EBC0_BNCR_BAS_ENCODE(0x94000000)    	| 	\	EBC0_BNCR_BS_1MB		    	|	\	EBC0_BNCR_BU_RW			    	|	\	EBC0_BNCR_BW_32BIT/* NAND1 - Bank3 */#define EBC0_BNCR_NAND_FLASH_CS3			\	EBC0_BNCR_BAS_ENCODE(0x94000000)    	| 	\	EBC0_BNCR_BS_1MB		    	|	\	EBC0_BNCR_BU_RW			    	|	\	EBC0_BNCR_BW_32BITint board_early_init_f(void){	ext_bus_cntlr_init();	/*--------------------------------------------------------------------	 * Setup the interrupt controller polarities, triggers, etc.	 *-------------------------------------------------------------------*/	mtdcr(uic0sr, 0xffffffff);	/* clear all */	mtdcr(uic0er, 0x00000000);	/* disable all */