-----------------------------------------------------------------------------------------
--
--       File Name: sdram_32.vhd
--       Version: 1.0
--       Date: November 14th, 2002
--       Model: Behavioral
--     	 Simulator: Active HDL 5.1
--
--       Author: Rafal Janta
--       Email:  rafal@alatek.com.pl
--       Company: ALATEK
--
--
--       Description: 64Mb SDRAM (512K x 32 x 4 Banks)
--
-----------------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity SDRAM_32 is
	port (
		CLK: IN STD_LOGIC;
		CKE: IN STD_LOGIC;
		nCS: IN STD_LOGIC;
		nRAS: IN STD_LOGIC;
		nCAS: IN STD_LOGIC;
		nWE: IN STD_LOGIC;
		BS: IN STD_LOGIC_VECTOR (1 downto  0);
		A: IN STD_LOGIC_VECTOR (10 downto  0);
		DQ_IN: IN STD_LOGIC_VECTOR (31 downto  0);
		DQ_OUT: OUT STD_LOGIC_VECTOR (31 downto  0);
		DQ_DiR: OUT STD_LOGIC_VECTOR (3 downto  0);	
		DQM: IN STD_LOGIC_VECTOR (3 downto  0)
	);
end SDRAM_32;


architecture BEH of SDRAM_32 is
	COMPONENT  mt48lc2m32b2  
	GENERIC (
        addr_bits : INTEGER := 11;
        data_bits : INTEGER := 32;
        col_bits  : INTEGER :=  8
    );
    PORT (
	    Dq_in     : IN  STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
        Dq_out    : OUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
        Dq_dir    : OUT STD_LOGIC_VECTOR (3 downto 0) := (OTHERS=>'0');
    	Addr      : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
        Ba        : IN    STD_LOGIC_VECTOR (1 downto 0) := "00";
        Clk       : IN    STD_LOGIC := '0';
        Cke       : IN    STD_LOGIC := '0';
        Cs_n      : IN    STD_LOGIC := '1';
        Ras_n     : IN    STD_LOGIC := '0';
        Cas_n     : IN    STD_LOGIC := '0';
        We_n      : IN    STD_LOGIC := '0';
        Dqm       : IN    STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0')  
    );
END COMPONENT;
begin

SDRAM:  mt48lc2m32b2  
PORT MAP(
	    Dq_in     => DQ_IN,
        Dq_out    => DQ_OUT,
        Dq_dir    => DQ_DIR,
    	Addr      => A,
        Ba        => BS,
		Clk       => CLK,
        Cke       => CKE,
        Cs_n      => nCS,
		Ras_n     => nRAS,
		Cas_n     => nCAS,
        We_n      => nWE,
        Dqm       => DQM
    );

	
end BEH;