---------------------------------------------------------------------------------------------------
--
-- Title       : SDR_CTRL
-- Design      : SDR_controller
-- Author      : Michal Krepa
-- Company     : XXX
--
---------------------------------------------------------------------------------------------------
--
-- File        : SDR_CTRL.vhd
-- Generated   : Tue Sep 16 10:07:58 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
--  Description : Single data rate SDRAM controller
--
---------------------------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


entity SDR_CTRL is
	generic(
		data_width: positive := 32;		-- host & SDRAM data width
		rows: positive := 2048;				-- number of rows in SDRAM array
		columns: positive := 256;				-- number of columns in SDRAM array
		haddr_width: positive := 21;		-- host-side address width
		saddr_width: positive := 11		-- SDRAM-side address width
	);
	port(	   
		-- host signals
		CLK : in STD_LOGIC;  
		nRST : in std_logic;
		ADDR : in std_logic_vector(haddr_width-1 downto 0);
		DATA_IN : in std_logic_vector(data_width-1 downto 0);
		nDTACK : out std_logic;
		WnR : in std_logic;
		nAS : in std_logic;
		nLBE : in std_logic_vector(data_width/8-1 downto 0);	
		-- sdram signals
		nCS : out STD_LOGIC;
		nRAS : out STD_LOGIC;
		nCAS : out STD_LOGIC;
		nWE : out STD_LOGIC;
		BS : out STD_LOGIC_vector(1 downto 0);
		CKE : out STD_LOGIC;
		DQM : out STD_LOGIC_VECTOR(data_width/8-1 downto 0);	
		DATA_OUT_SDR : out std_logic_vector(data_width-1 downto 0);
		A : out STD_LOGIC_VECTOR(saddr_width-1 downto 0)
		);
end SDR_CTRL;

architecture SDR_CTRL of SDR_CTRL is   
	
	function log2(v: in natural) return natural is
		variable n: natural;
		variable logn: natural;
	begin
		n := 1;
		for i in 0 to 128 loop
			logn := i;
			exit when (n>=v);
			n := n * 2;
		end loop;
		return logn;
	end function log2;
	
	constant CLOCK_PERIOD : positive := 30; -- in ns
	-- burst size	   		 
	constant burst : positive := 8;	
	-- enable/disable autoprecharge = 1/0
	constant auto_precharge : std_logic := '0';		  
	-- init refresh cycles
	constant init_ref_cycles : natural := 2;  
	
	constant row_length: natural := log2(rows);	-- number of row address bits
	constant column_length:	natural := log2(columns);	-- number of column address bits
	
	
	-- timing constants in ns:
	--constant tRC  : positive := 65;
	constant tRCD : positive := 20;
	constant tRP  : positive := 20;
	constant tREF : positive := 15000; -- for 1 row (for 4096 you need to divide number by 4096)        
	constant tRFC : positive := 65; 
	constant tWR  : positive := CLOCK_PERIOD + 7; 
	-- sdram initialization time
	-- fo eg.: if 100 us sdram initialization is needed, tSTARTUP_NOP should be 100000 [ns]
	constant tSTARTUP_NOP : positive := 100000;
	
	-- timing constants in cycles
	-- actual cycles will be one cycle longer (every) because of state transition time (1 cycle time)
	--constant tRC_CYCLES  : natural := tRC  / CLOCK_PERIOD;	 -- tRC_time = tRC_CYCLES + 1
	constant tRCD_CYCLES : natural := tRCD / CLOCK_PERIOD;	 --	tRCD_time = tRCD_CYCLES + 1
	constant tRP_CYCLES  : natural := tRP  / CLOCK_PERIOD;	 -- tRP_time = tRP_CYCLES + 1
	constant tMRD_CYCLES : natural := 2; 					 -- tMRD_time = 2 tCK
	constant tREF_CYCLES : natural := tREF / CLOCK_PERIOD;	 --	tREF_time = tREF_CYCLES + 1
	constant tRFC_CYCLES : NATURAL := tRFC / CLOCK_PERIOD;	 -- tRFC_time = tRFC_CYCLES + 1
	constant tWR_CYCLES  : natural := tWR / CLOCK_PERIOD; 	 --	tWR_time = tWR_CYCLES + 1
	constant tSTARTUP_NOP_CYCLES : positive := tSTARTUP_NOP / (2*CLOCK_PERIOD);	 
	
	constant burst_size : std_logic_vector(2 downto 0) := conv_std_logic_vector(log2(burst),3);
	constant CAS_LATENCY : positive := 2; 
	
	-- specified to supress simulation warnings from micron sdram models
	constant hold_time: time:= 2 ns;
	
	type state_type is (
	initialize,
	active, 
	read_data,
	read,
	write,
	set_ModeRegister,
	precharge,
	auto_refresh,
	nop 
	);
	signal state : state_type;
	
	signal refresh_req      : std_logic;  -- Refresh request signals
	signal refresh_done_flg : std_logic; 
	signal refresh_timer : integer range 0 to tREF_CYCLES; 
	signal startup_timer : integer range 0 to tSTARTUP_NOP_CYCLES; 
	
	signal startup_pending : std_logic;	-- '1' - in startup sequence
	signal wait_counter : integer range 0 to 31; -- how many cycles wait until next command can be issued
	signal init_refreshes : integer range 0 to init_ref_cycles; -- autorefresh commands needed in startup sequence
	signal nAS_WAITING	: std_logic; -- if read/write is waiting to be executed
	signal CAS_counter : integer range 0 to 3;
	signal execute_nop : std_logic;
	signal nLBE_s : std_logic_vector(data_width/8-1 downto 0);
	signal aref_enable : std_logic;	-- autorefresh enable
	
	signal bank_numb	 : std_logic_vector(BS'range);
	signal row_addr		 : std_logic_vector(row_length-1 downto 0);
	signal col_addr		 : std_logic_vector(column_length-1 downto 0);
	signal WnR_S		 : std_logic;   
	signal burst_counter : integer range 0 to 7;	
	
begin	
	-- Hold nAS	  
	-- nAS - active low address strobe
	ADS_DETECT: process(nRST, CLK)
	begin
		if nRST = '0' then
			nAS_WAITING <= '0';
			bank_numb <= (others => '0');  
			col_addr <= (others => '0');   
			row_addr <= (others => '0'); 
			DATA_OUT_SDR <= (others => '0'); 
			nLBE_s <= (others => '1');
		elsif rising_edge(CLK) then	 
			-- if address strobe latch address
			if nAS='0' then
				nAS_WAITING <= '1';	 
				bank_numb <= ADDR(BS'length + row_length + column_length - 1 downto row_length + column_length) after hold_time;	 
				row_addr <= ADDR(row_length+column_length-1 downto column_length) after hold_time;	
				col_addr <= ADDR(column_length-1 downto 0) after hold_time;
				DATA_OUT_SDR <= DATA_IN after hold_time;
				nLBE_s <= nLBE;
			elsif state = active then
				nAS_WAITING <= '0';
			end if;
		end if;
	end process;
	
	sdram_ctrl : process(CLK, nRST)
	begin		
		if nRST = '0' then
			CKE <= '0';	
			DQM <= (others => '1');	
			nCS <= '1';
			nRAS <= '1';
			nCAS <= '1'; 
			nWE <= '1';
			BS <= "00";
			A <= (others => '0');		
			state <= initialize; 
			startup_pending <= '1';	
			wait_counter <= 0;	 
			init_refreshes <= 0;
			nDTACK <= '1';	
			CAS_counter <= 0;  
			burst_counter <= 0;
			startup_timer <= 0;
			refresh_done_flg <= '0';
			WnR_S <= '0';  
			execute_nop <= '0';	 
			aref_enable <= '1';	
		elsif rising_edge(CLK) then
			
			case state is		 
				--------------------------
				-- initialization		 
				--------------------------
				when initialize =>
				CKE <= '1';	
				nCS <= '0';
				state <= nop after hold_time;	
				
				-----------------------------
				-- MODE REGISTER SET command
				-----------------------------
				when set_ModeRegister =>
				nCS  <= '0' after hold_time;
				nRAS <= '0' after hold_time;
				nCAS <= '0' after hold_time;
				nWE  <= '0' after hold_time;
				A <= 
				 '0'	-- should be '0' to ensure compability with future devices
				& '1'	 					-- write burst mode: '0' - programmed burst length; '1' - single acces location
				& "00" 						-- operation mode: "00" - standard; others - reserved
				& conv_std_logic_vector(CAS_Latency,3) -- CAS Latency
				& '0'						-- Burst Mode: '0' - sequence; '1' - interleave
				& burst_size; 					-- BURST LENGTH	of 8 
				-- after MRS command issue n nop cycles where n = tMRD_CYCLES 
				if execute_nop = '1' then
					nCS <= '0' after hold_time;
					nRAS <= '1' after hold_time;
					nCAS <= '1' after hold_time;
					nWE <= '1' after hold_time;		
				end if;
				
				-- wait for tMRD_CYCLES before issue
				if wait_counter < tMRD_CYCLES then
					wait_counter <= wait_counter + 1; 
					execute_nop <= '1';
				else			
					-- sdram initialization complete
					wait_counter <= 0;	
					startup_pending <= '0';	
					nDTACK <= '0' after hold_time;
					state <= nop after hold_time;	
					execute_nop <= '0';
				end if;	
				
				--------------------------
				-- NOP command			 
				--------------------------
				when nop =>
				nCS <= '0' after hold_time;
				nRAS <= '1' after hold_time;
				nCAS <= '1' after hold_time;
				nWE <= '1' after hold_time;		 
				DQM <= (others => '0') after hold_time;	
				WnR_S <= WnR after hold_time;  
				
				execute_nop <= '0';	
				nDTACK <= '1' after hold_time;