?? mt48lc2m32b2_2.vhd
字號:
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC2M32B2.VHD
-- Version: 1.0
-- Date: Sept 10th, 2001
-- Model: Behavioral
-- Simulator: Model Technology
--
-- Dependencies: None
--
-- Author: Yong Phan
-- Email: yjphan@micron.com
-- Phone: (208) 363-2184
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC2M32B2 (512K x 32 x 4 Banks)
--
-- Description: Micron 64Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 2001 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone/Mail Date Changes
-- --- -------------- -------------- ---------- -------------------------------------
-- 3.0 Rafal Janta rafal@alatek.com.pl 11/12/2002 - Disjoin data bus
-- Alatek
--
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 05/19/2000 Fix tWR + tRP timing
-- Micron Technology Inc.
-- 1.0 Yong Phan 208-363-2184 09/10/2001 Add Load/Unload Function
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY std;
USE std.textio.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.conv_integer;
USE ieee.std_logic_arith.conv_std_logic_vector;
ENTITY mt48lc2m32b2 IS
GENERIC (
-- Timing Parameters for -6 and CAS Latency = 2
tOH : TIME := 2.0 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 42.0 ns;
tRC : TIME := 60.0 ns;
tRCD : TIME := 18.0 ns;
tRP : TIME := 18.0 ns;
tRRD : TIME := 12.0 ns;
tWRa : TIME := 6.0 ns; -- A2 Version - Auto precharge mode only (1 Clk + 6 ns)
tWRp : TIME := 12.0 ns; -- A2 Version - Precharge mode only (12 ns)
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.5 ns;
tDH : TIME := 1.0 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 1.0 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0 ns;
tCMS : TIME := 0 ns;
addr_bits : INTEGER := 11;
data_bits : INTEGER := 32;
col_bits : INTEGER := 8
);
PORT (
Dq_in : IN STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dq_out : OUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dq_dir : OUT STD_LOGIC_VECTOR (3 downto 0) := (OTHERS=>'0');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '0';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '0';
Cas_n : IN STD_LOGIC := '0';
We_n : IN STD_LOGIC := '0';
Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0')
);
END mt48lc2m32b2;
ARCHITECTURE behave OF mt48lc2m32b2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, FILE_LOAD, FILE_UNLOAD);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xSL IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array4x2SLV IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); -- For Bank Pipeline
TYPE Array2x4SLV IS ARRAY (1 DOWNTO 0) OF STD_LOGIC_VECTOR (3 DOWNTO 0); -- For Dqm Pipeline
TYPE Array4xCSLV IS ARRAY (4 DOWNTO 0) OF STD_LOGIC_VECTOR (Col_bits - 1 DOWNTO 0); -- For Column Pipeline
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : STD_LOGIC := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : STD_LOGIC := '0';
SIGNAL Cas_latency_1, Cas_latency_2, Cas_latency_3 : STD_LOGIC := '0';
SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
SIGNAL Write_burst_mode : STD_LOGIC := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : STD_LOGIC := '0';
BEGIN
-- Strip the strength
Cs_in <= To_X01 (Cs_n);
Ras_in <= To_X01 (Ras_n);
Cas_in <= To_X01 (Cas_n);
We_in <= To_X01 (We_n);
-- Commands Decode
Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_1 <= NOT(Mode_reg(6)) AND NOT(Mode_reg(5)) AND Mode_reg(4);
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN
CkeZ <= Cke;
END IF;
Sys_clk <= CkeZ AND Clk;
END PROCESS;
state_register : PROCESS
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCSLV;
VARIABLE Bank_addr : Array4x2SLV;
VARIABLE Dqm_reg0, Dqm_reg1 : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
VARIABLE Bank, Previous_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2SLV;
VARIABLE A10_precharge : Array4xSL := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xSL := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xSL := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xSL := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xSL := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xSL := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Unload variables
VARIABLE l_in, l_out0, l_out1, l_out2, l_out3 : LINE;
VARIABLE array_buffer : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE row_load : BIT_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE col_load : BIT_VECTOR (col_bits - 1 DOWNTO 0);
VARIABLE ba_load : BIT_VECTOR (1 DOWNTO 0);
VARIABLE dq_vec : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
VARIABLE row_load_int,i, j, k : INTEGER;
-- Initialize empty rows
PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : STD_LOGIC_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := conv_integer(Col) + 1;
Col_temp := CONV_STD_LOGIC_VECTOR(Col_int, col_bits);
ELSIF Mode_reg (3) = '1' THEN
Col_vec := CONV_STD_LOGIC_VECTOR(Burst_counter, col_bits);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
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