?? mt48lc2m32b2_2.vhd
字號:
Dq_dir <= "0000";
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := CONV_INTEGER (Row);
Col_index := CONV_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "1111" THEN
-- Initialize memory
Init_mem (Bank, Row_index);
-- Load memory into buffer
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
END IF;
-- Dqm operation
IF Dqm (0) = '0' THEN
Dq_temp (7 DOWNTO 0) := Dq_in (7 DOWNTO 0);
END IF;
IF Dqm (1) = '0' THEN
Dq_temp (15 DOWNTO 8) := Dq_in (15 DOWNTO 8);
END IF;
IF Dqm (2) = '0' THEN
Dq_temp (23 DOWNTO 16) := Dq_in (23 DOWNTO 16);
END IF;
IF Dqm (3) = '0' THEN
Dq_temp (31 DOWNTO 24) := Dq_in (31 DOWNTO 24);
END IF;
-- Write back to memory
IF Bank = "00" THEN
Bank0 (Row_index) (Col_index) := Dq_temp;
ELSIF Bank = "01" THEN
Bank1 (Row_index) (Col_index) := Dq_temp;
ELSIF Bank = "10" THEN
Bank2 (Row_index) (Col_index) := Dq_temp;
ELSIF Bank = "11" THEN
Bank3 (Row_index) (Col_index) := Dq_temp;
END IF;
-- Reset tWR counter
WR_chkp(CONV_INTEGER(Bank)) := NOW;
WR_counter(CONV_INTEGER(Bank)) := 0;
END IF;
-- Decode next burst address
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "1111" THEN
-- Initialize memory
Init_mem (Bank, Row_index);
-- Load memory into buffer
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
END IF;
-- Dqm operation
IF Dqm_reg0 (0) = '0' THEN
Dq_out (7 DOWNTO 0) <= Dq_temp(7 DOWNTO 0);
Dq_dir(0) <= '1';
ELSE
Dq_dir(0) <= '0';
END IF;
IF Dqm_reg0 (1) = '0' THEN
Dq_out (15 DOWNTO 8) <= Dq_temp(15 DOWNTO 8);
Dq_dir(1) <= '1';
ELSE
Dq_dir(1) <= '0';
END IF;
IF Dqm_reg0 (2) = '0' THEN
Dq_out (23 DOWNTO 16) <= Dq_temp(23 DOWNTO 16);
Dq_dir(2) <= '1';
ELSE
Dq_dir(2) <= '0';
END IF;
IF Dqm_reg0 (3) = '0' THEN
Dq_out (31 DOWNTO 24) <= Dq_temp(31 DOWNTO 24);
Dq_dir(3) <= '1';
ELSE
Dq_dir(3) <= '0';
END IF;
ELSE
Dq_out <= (OTHERS => 'Z');
Dq_dir <= "0000";
END IF;
Burst_decode;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
END IF;
END PROCESS;
-- Clock timing checks
Clock_check : PROCESS
VARIABLE Clk_low, Clk_high : TIME := 0 ns;
BEGIN
WAIT ON Clk;
IF (Clk = '1' AND NOW >= 10 ns) THEN
ASSERT (NOW - Clk_low >= tCL)
REPORT "tCL violation"
SEVERITY WARNING;
ASSERT (NOW - Clk_high >= tCK)
REPORT "tCK violation"
SEVERITY WARNING;
Clk_high := NOW;
ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
ASSERT (NOW - Clk_high >= tCH)
REPORT "tCH violation"
SEVERITY WARNING;
Clk_low := NOW;
END IF;
END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS)
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS)
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS)
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS)
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS)
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS)
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS)
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS)
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq_in'LAST_EVENT >= tDS)
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN
ASSERT(Cke'LAST_EVENT > tCKH)
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN
ASSERT(Cs_n'LAST_EVENT > tCMH)
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH)
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH)
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH)
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH)
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN
ASSERT(Dq_in'LAST_EVENT > tDH)
REPORT "DQ Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
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