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--
-- Title       : Test Bench for sdram_top
-- Design      : SDR_controller
-- Author      : Michal Krepa
-- Company     : XXX
--
---------------------------------------------------------------------------------------------------
--
-- File        : $DSN\src\TestBench\sdram_top_TB.vhd
-- Generated   : 2003-09-17, 10:35
-- From        : $DSN\compile\sdram_top.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
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--
-- Description : Automatically generated Test Bench for sdram_top_tb
--
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library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- Add your library and packages declaration here ...

entity sdram_top_tb is
end sdram_top_tb;

architecture TB_ARCHITECTURE of sdram_top_tb is
	-- Component declaration of the tested unit
	component sdram_top
		port(
			CLK : in std_logic;
			WnR : in std_logic;
			nAS : in std_logic;
			nRST : in std_logic;
			ADDR : in std_logic_vector(20 downto 0);
			DIN : in std_logic_vector(31 downto 0);
			nLBE : in std_logic_vector(3 downto 0);
			nDTACK : out std_logic;
			DOUT : out std_logic_vector(31 downto 0) );
	end component;
	
	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal CLK : std_logic;
	signal WnR : std_logic;
	signal nAS : std_logic;
	signal nRST : std_logic;
	signal ADDR : std_logic_vector(20 downto 0);
	signal DIN : std_logic_vector(31 downto 0);
	signal nLBE : std_logic_vector(3 downto 0);
	-- Observed signals - signals mapped to the output ports of tested entity
	signal nDTACK : std_logic;
	signal DOUT : std_logic_vector(31 downto 0);
	
	--Signal is used to stop clock signal generators
	signal END_SIM: BOOLEAN:=FALSE;			  
	constant hold_time : time := 2 ns;
	
begin
	
	-- Unit Under Test port map
	UUT : sdram_top
	port map (
		CLK => CLK,
		WnR => WnR,
		nAS => nAS,
		nRST => nRST,
		ADDR => ADDR,
		DIN => DIN,
		nLBE => nLBE,
		nDTACK => nDTACK,
		DOUT => DOUT
		);
	
	--Below VHDL code is an inserted .\compile\Waveform Editor 3.vhs
	--User can modify it ....
	
	STIMULUS: process	  
	variable ix : integer := 0;	  
	variable burst : integer := 8;
	begin  -- of stimulus process
		--wait for <time to next event>; -- <current time>
		
		DIN <= "00000111010110111100110100010101";
		ADDR <= "000000000000000110010";
		nRST <= '0';
		nLBE <= "0000";
		wait for 100 ns; --0 fs
		nRST <= '1';  
		wait until nDTACK = '0';
		WnR <= '1';	
		wait for 60 ns;
		
		for i in 0 to 2000 loop
			DIN <= conv_std_logic_vector(i,32);
			ADDR <= conv_std_logic_vector(i,21);
			--wait for 136 ns;
			nAS <= '0';
			wait for 31 ns;
			nAS <= '1';	  
			while nDTACK /= '0' loop
				wait until rising_edge(CLK);
				if nDTACK = '0' then
					exit;
				end if;
			end loop;
			
			while nDTACK /= '1' loop
				wait until rising_edge(CLK);
				if nDTACK = '1' then
					exit;
				end if;
			end loop;
		end loop;		
		
		wait for 30 ns;
		
		WnR <= '0';

	   	for i in 0 to (2000/burst+burst) loop
			ADDR <= conv_std_logic_vector(ix,21);
			nAS <= '0';
			wait for 31 ns;
			nAS <= '1';	  
			while nDTACK /= '0' loop
				wait until rising_edge(CLK);
				if nDTACK = '0' then
					exit;
				end if;
			end loop;
			
			while nDTACK /= '1' loop
				wait until rising_edge(CLK);
				if nDTACK = '1' then
					exit;
				end if;
			end loop;  
			
			ix := ix + burst;
			
		end loop;	
		
		wait for 590 ms; --100 ns
		END_SIM <= TRUE;
		--	end of stimulus events
		wait;
	end process; -- end of stimulus process
	
	CLOCK_CLK : process
	begin
		--this process was generated based on formula: 1 0 fs, 0 15151515 fs -r 30303030 fs
		--wait for <time to next event>; -- <current time>
		if END_SIM = FALSE then
			CLK <= '1';
			wait for 15151 ps; --0 fs
		else
			wait;
		end if;
		if END_SIM = FALSE then
			CLK <= '0';
			wait for 15152 ps; --15151 ps
		else
			wait;
		end if;
	end process;
	
	
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_sdram_top of sdram_top_tb is
	for TB_ARCHITECTURE
		for UUT : sdram_top
			use entity work.sdram_top(sdram_top);
		end for;
	end for;
end TESTBENCH_FOR_sdram_top;