;******************************************************************************
;   MSP-FET430x110 Demo - Software SPI Interface to TLV5616 12-Bit DAC
;
;   Description: Drive serial communications with TLV5616 12-bit DAC. A sine
;   wave is generated using a a 32-step sine look-up table Sin_Tab. R5 is
;   used as a pointer into Sin_Tab, R6 holds the 12-bit data and R7 is used
;   as a temporary bit counter.
;   ACLK = n/a, MCLK = SMCLK = default DCO ~800k
;
;                 MSP430F1121
;             -----------------
;        /|\ |              XIN|-
;         |  |                 |      TLV5616
;         ---|RST          XOUT|-   ----------
;            |             P2.3|-->|FS     OUT|--> ~75hz sine wave
;            |             P2.0|-->|DIN       |
;            |             P2.1|-->|SCLK    CS|-|
;            |                 |   |          | v
;
DOUT        EQU     001h                    ; P2.0 Data Out
SCLK        EQU     002h                    ; P2.1 Serial Clock
FS          EQU     008h                    ; P2.3 Frame Sync
;
;   M. Buccini
;   Texas Instruments Inc.
;   Feb 2005
;   Built with IAR Embedded Workbench Version: 3.21A
;*****************************************************************************
#include  <msp430x11x1.h>
;------------------------------------------------------------------------------
            ORG     0F000h                  ; Program Start
;------------------------------------------------------------------------------
RESET       mov.w   #0300h,SP               ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop Watchdog Timer
SetupP1     bis.b   #FS+SCLK,&P2OUT         ; FS, SCLK Set
            bis.b   #FS+SCLK+DOUT,&P2DIR    ; FS,Clk and DOUT as outputs
                                            ;
Mainloop    incd.w  R5                      ; R5 = sine table pointer
            and.w   #03Eh,R5                ; 32 steps in table
            mov.w   Sin_tab(R5),R6          ; R6 = Sine value
                                            ;
            bic.b   #FS,&P2OUT              ; FS low, enable DAC
            mov.w   #16,R7                  ; R7 = 16 bits to shift out
DAC_Loop    rlc.w   R6                      ; C = Data bit
Out_0       bic.b   #DOUT,&P2OUT            ; DOUT reset
            jnc     Clk_0                   ;
Out_1       bis.b   #DOUT,&P2OUT            ; DOUT set
Clk_0       bic.b   #SCLK,&P2OUT            ; SCLK reset, data latched
            dec.w   R7                      ;
Clk_1       bis.b   #SCLK,&P2OUT            ; SCLK set
            jnz     DAC_Loop                ;
            bis.b   #FS,&P2OUT              ; FS high, disable DAC
            jmp     Mainloop                ; Repeat
                                            ;
;------------------------------------------------------------------------------
; 12-bit Sine Lookup table with 32 steps
;------------------------------------------------------------------------------
Sin_tab     DW       2048
            DW       2447
            DW       2831
            DW       3185
            DW       3495
            DW       3750
            DW       3939
            DW       4056
            DW       4095
            DW       4056
            DW       3939
            DW       3750
            DW       3495
            DW       3185
            DW       2831
            DW       2447
            DW       2048
            DW       1648
            DW       1264
            DW       910
            DW       600
            DW       345
            DW       156
            DW       39
            DW       0
            DW       39
            DW       156
            DW       345
            DW       600
            DW       910
            DW       1264
            DW       1648
;
;------------------------------------------------------------------------------
;           Interrupt Vectors
;------------------------------------------------------------------------------
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ;
            END