?? mc8051_siu.vhd
字號:
if s_m2_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0101") => -- D5
if s_m2_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0110") => -- D6
if s_m2_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0111") => -- D7
if s_m2_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("1000") => -- D8
if s_m2_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("1001") => -- D9
if s_m2_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("1010") => -- D10, set done bit
if s_m2_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
s_tran_done <= '1';
v_txstep := "10";
s_txdm0 <= s_tran_sh(1);
end if;
when others => -- D0
-- commence transmission if conditions are met
s_txdm0 <= '1';
if s_m2_txshift_en = '1' then
if s_trans = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9) <= s_tb8;
s_tran_sh(8 downto 1) <= unsigned(sbuf_i);
s_tran_sh(0) <= '0';
v_txstep := "01";
s_tran_done <= '0';
s_txdm0 <= '0';
end if;
end if;
end case;
-------------------------------------------------------------------------------
-- MODE 3
-------------------------------------------------------------------------------
when ("11") =>
rxd_o <= '0';
rxdwr_o <= '0';
case s_tran_state is
when ("0001") => -- D1
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0010") => -- D2
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0011") => -- D3
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0100") => -- D4
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0101") => -- D5
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0110") => -- D6
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("0111") => -- D7
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("1000") => -- D8
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("1001") => -- D9
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
v_txstep := "01";
s_txdm0 <= s_tran_sh(1);
end if;
when ("1010") => -- D10, set done bit
if s_m13_txshift_en = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);
s_tran_done <= '1';
v_txstep := "10";
s_txdm0 <= s_tran_sh(1);
end if;
when others => -- D0
-- commence transmission if conditions are met
s_txdm0 <= '1';
if s_m13_txshift_en = '1' then
if s_trans = '1' then
s_tran_sh(10) <= '1';
s_tran_sh(9) <= s_tb8;
s_tran_sh(8 downto 1) <= unsigned(sbuf_i);
s_tran_sh(0) <= '0';
s_tran_done <= '0';
v_txstep := "01";
s_txdm0 <= '0';
end if;
end if;
end case;
-------------------------------------------------------------------------------
when others =>
null;
end case;
case v_txstep is
when "01" =>
s_tran_state <= s_tran_state + conv_unsigned(1, 1);
when "10" =>
s_tran_state <= conv_unsigned(0, 4);
when others =>
null;
end case;
end if;
end if;
end process p_transmit;
-------------------------------------------------------------------------------
--**************************** RECEIVE ****************************************
-- This is the finit state machine for the receive shift register
-------------------------------------------------------------------------------
p_receive: process (clk,
reset)
variable v_rxstep : std_logic_vector(1 downto 0);
begin
if reset = '1' then
s_recv_state <= conv_unsigned(0,4);
s_recv_sh <= conv_unsigned(0,8);
s_recv_buf <= conv_unsigned(0,8);
s_recv_done <= '0';
s_rb8 <= '0';
else
if clk'event and clk = '1' then
-------------------------------------------------------------------------------
-- MODE 0
-------------------------------------------------------------------------------
v_rxstep := "00";
case s_mode is
when ("00") =>
case s_recv_state is
when ("0000") => -- D0
-- commence reception if conditions are met
if s_ren = '1' and s_ri = '0' then
if s_m0_shift_en = '1' then
v_rxstep := "01";
s_recv_done <= '0';
end if;
end if;
when ("0001") => -- D1
if s_m0_shift_en = '1' then
s_recv_sh(7) <= rxd_i;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0010") => -- D2
if s_m0_shift_en = '1' then
s_recv_sh(7) <= rxd_i;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0011") => -- D3
if s_m0_shift_en = '1' then
s_recv_sh(7) <= rxd_i;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0100") => -- D4
if s_m0_shift_en = '1' then
s_recv_sh(7) <= rxd_i;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0101") => -- D5
if s_m0_shift_en = '1' then
s_recv_sh(7) <= rxd_i;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0110") => -- D6
if s_m0_shift_en = '1' then
s_recv_sh(7) <= rxd_i;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0111") => -- D6
if s_m0_shift_en = '1' then
s_recv_sh(7) <= rxd_i;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1000") => -- D7, set bits and store data
if s_m0_shift_en = '1' then
s_recv_sh(7) <= rxd_i;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
s_recv_done <= '1';
s_recv_buf(7) <= rxd_i;
s_recv_buf(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "10";
end if;
when others =>
v_rxstep := "10";
end case;
-------------------------------------------------------------------------------
-- MODE 1
-------------------------------------------------------------------------------
when ("01") =>
case s_recv_state is
when ("0000") => -- synchronise reception
if s_ren = '1' and s_detect = '1' then
v_rxstep := "01";
s_recv_sh <= conv_unsigned(0,8);
s_recv_done <= '0';
end if;
when ("0001") => -- D0 = START BIT
if s_detect = '0' then
if s_rxd_val = '0' then
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
else -- reject false start bits
if s_m13_rxshift_en = '1' then
v_rxstep := "10";
end if;
end if;
end if;
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