?? control_mem.vhd
字號:
-------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.mc8051_p.all;
entity control_mem is
port (pc_o : out std_logic_vector(15 downto 0); -- Programmcounter =
-- ROM-adress
rom_data_i : in std_logic_vector(7 downto 0); -- data input from ROM
ram_data_o : out std_logic_vector(7 downto 0); -- data output to
-- internal RAM
ram_data_i : in std_logic_vector(7 downto 0); -- data input from
-- internal RAM
ram_adr_o : out std_logic_vector(6 downto 0); -- internal RAM-adress
reg_data_o : out std_logic_vector(7 downto 0); -- data for ALU
ram_wr_o : out std_logic; -- read (0) / write (1)
-- internal RAM
cy_o : out std_logic_vector(1 downto 0); -- Carry Flag
ov_o : out std_logic; -- Overflow Flag
ram_en_o : out std_logic; -- RAM-block enable
aludata_i : in std_logic_vector (7 downto 0); -- ALU result
aludatb_i : in std_logic_vector (7 downto 0); -- 2nd ALU result
acc_o : out std_logic_vector (7 downto 0); -- ACC register
new_cy_i : in std_logic_vector(1 downto 0); -- CY result of ALU
new_ov_i : in std_logic; -- OV result of ALU
reset : in std_logic; -- reset signal
clk : in std_logic; -- clock signal
int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); -- ext.Int
int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0); -- ext.Int
p0_i : in std_logic_vector(7 downto 0); -- IO-port0
p1_i : in std_logic_vector(7 downto 0); -- IO-port1
p2_i : in std_logic_vector(7 downto 0); -- IO-port2
p3_i : in std_logic_vector(7 downto 0); -- IO-port3
p0_o : out std_logic_vector(7 downto 0); -- IO-port0
p1_o : out std_logic_vector(7 downto 0); -- IO-port1
p2_o : out std_logic_vector(7 downto 0); -- IO-port2
p3_o : out std_logic_vector(7 downto 0); -- IO-port3
-- Signals to and from the SIUs
-- "1" starts serial transmission in SIU
all_trans_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
-- RI,SM0,SM1,SM2,REN,TB8
all_scon_o : out std_logic_vector(6*C_IMPL_N_SIU-1 downto 0);
-- data buffer for SIU
all_sbuf_o : out std_logic_vector(8*C_IMPL_N_SIU-1 downto 0);
-- baud rate for SIU in PCON
all_smod_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
-- RB8, TI, RI of SIU
all_scon_i : in std_logic_vector(3*C_IMPL_N_SIU-1 downto 0);
-- int. data buffer of SIU
all_sbuf_i : in std_logic_vector(8*C_IMPL_N_SIU-1 downto 0);
-- signals to and from the timer/counters
-- timer run flag0 of T/C
all_tcon_tr0_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
-- timer run flag1 of T/C
all_tcon_tr1_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
-- TMOD for T/C
all_tmod_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
-- user reload value for T/C
all_reload_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
-- reload enable for T/C
all_wt_o : out std_logic_vector(2*C_IMPL_N_TMR-1 downto 0);
-- reload target for T/C
all_wt_en_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
-- timer OF flag0 of T/C
all_tf0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
-- timer OF flag1 of T/C
all_tf1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
-- count value of T/C
all_tl0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
-- count value of T/C
all_tl1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
-- count value of T/C
all_th0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
-- count value of T/C
all_th1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
-- signals from/to the state-machine
state_o : out t_state; -- actual state
help_o : out std_logic_vector(7 downto 0); -- general help-reg
bit_data_o : out std_logic; -- bitdata from regs
command_o : out std_logic_vector (7 downto 0); -- actual command
inthigh_o : out std_logic; -- high priority int is running
intlow_o : out std_logic; -- low priority int is running
intpre_o : out std_logic; -- an interrupt must start
intpre2_o : out std_logic; -- prepare for interrupt
intblock_o : out std_logic; -- interrupt delay at RETI, IE, IP
ti_o : out std_logic;
ri_o : out std_logic;
ie0_o : out std_logic;
ie1_o : out std_logic;
tf0_o : out std_logic;
tf1_o : out std_logic;
psw_o : out std_logic_vector(7 downto 0);
ie_o : out std_logic_vector(7 downto 0);
ip_o : out std_logic_vector(7 downto 0);
adrx_o : out std_logic_vector(15 downto 0); -- ext. RAM
datax_o : out std_logic_vector(7 downto 0); -- ext. RAM
wrx_o : out std_logic; -- ext. RAM
datax_i : in std_logic_vector(7 downto 0); -- ext. RAM
pc_inc_en_i : in std_logic_vector (3 downto 0);
nextstate_i : in t_state; -- enable signal for state
adr_mux_i : in std_logic_vector (3 downto 0);
adrx_mux_i : in std_logic_vector (1 downto 0);
wrx_mux_i : in std_logic;
data_mux_i : in std_logic_vector (3 downto 0);
bdata_mux_i : in std_logic_vector (3 downto 0);
regs_wr_en_i : in std_logic_vector (2 downto 0);
help_en_i : in std_logic_vector (3 downto 0);
help16_en_i : in std_logic_vector (1 downto 0);
helpb_en_i : in std_logic;
inthigh_en_i : in std_logic;
intlow_en_i : in std_logic;
intpre2_en_i : in std_logic;
inthigh_d_i : in std_logic;
intlow_d_i : in std_logic;
intpre2_d_i : in std_logic;
ext0isr_d_i : in std_logic;
ext1isr_d_i : in std_logic;
ext0isrh_d_i : in std_logic;
ext1isrh_d_i : in std_logic;
ext0isr_en_i : in std_logic;
ext1isr_en_i : in std_logic;
ext0isrh_en_i : in std_logic;
ext1isrh_en_i : in std_logic);
end control_mem;
-------------------------------------------------------------------------------
architecture rtl of control_mem is
type t_gprbit is array (15 downto 0) of unsigned(7 downto 0);
subtype muxint is integer range C_IMPL_N_TMR-1 downto 0;
signal s_help: unsigned (7 downto 0); -- general help-register
signal s_help16: unsigned (15 downto 0); -- 16 bit help-register
signal s_helpb : std_logic; -- general help-bit
signal s_ir: unsigned (7 downto 0); -- reg for saving the command
signal gprbit: t_gprbit; -- bitadressable general purpose RAM
signal s_r0_b0: unsigned (7 downto 0); -- Register R0 / Bank 0
signal s_r1_b0: unsigned (7 downto 0); -- Register R1 / Bank 0
signal s_r0_b1: unsigned (7 downto 0); -- Register R0 / Bank 1
signal s_r1_b1: unsigned (7 downto 0); -- Register R1 / Bank 1
signal s_r0_b2: unsigned (7 downto 0); -- Register R0 / Bank 2
signal s_r1_b2: unsigned (7 downto 0); -- Register R1 / Bank 2
signal s_r0_b3: unsigned (7 downto 0); -- Register R0 / Bank 3
signal s_r1_b3: unsigned (7 downto 0); -- Register R1 / Bank 3
signal s_reg_data: unsigned (7 downto 0); -- equals reg_data_o
Signal state: t_state; -- actual state
signal s_command: std_logic_vector (7 downto 0);
signal s_pc_inc_en : std_logic_vector (3 downto 0);
signal s_regs_wr_en : std_logic_vector (2 downto 0);
signal s_data_mux : std_logic_vector (3 downto 0);
signal s_bdata_mux : std_logic_vector (3 downto 0);
signal s_adr_mux : std_logic_vector (3 downto 0);
signal s_adrx_mux : std_logic_vector (1 downto 0);
signal s_help_en : std_logic_vector (3 downto 0);
signal s_help16_en : std_logic_vector (1 downto 0);
signal s_helpb_en : std_logic;
signal s_intpre2_d : std_logic;
signal s_intpre2_en: std_logic;
signal s_intlow_d : std_logic;
signal s_intlow_en : std_logic;
signal s_inthigh_d : std_logic;
signal s_inthigh_en: std_logic;
signal s_ext0isr_d : std_logic;
signal s_ext0isrh_d : std_logic;
signal s_ext1isr_d : std_logic;
signal s_ext1isrh_d : std_logic;
signal s_nextstate : t_state; -- enable signal for state
signal s_bit_data : std_logic;
signal s_intpre: std_logic; -- an interrupt must start
signal s_intpre2: std_logic; -- prepare for interrupt
signal s_inthigh: std_logic; -- high priority int is running
signal s_intlow: std_logic; -- low priority int is running
signal s_intblock: std_logic; -- interrupt delay at RETI, IE, IP
signal s_int0_edge : t_ext_l;
signal s_int1_edge : t_ext_l;
signal s_tf0_edge : t_tmr_l;
signal s_tf1_edge : t_tmr_l;
signal s_ri_edge : t_siu_l;
signal s_ti_edge : t_siu_l;
signal s_smodreg : t_siu_l;
signal s_tl0 : t_tmr_us;
signal s_tl1 : t_tmr_us;
signal s_th0 : t_tmr_us;
signal s_th1 : t_tmr_us;
signal s_sbufi : t_siu_us;
signal s_reload : t_tmr_us;
signal s_wt : t_tmr_us2;
signal s_tf1 : std_logic;
signal s_tf0 : std_logic;
signal s_ie1 : std_logic;
signal s_ie0 : std_logic;
signal s_ri : std_logic;
signal s_ti : std_logic;
signal s_rb8 : std_logic;
signal s_tb8 : std_logic;
signal s_ren : std_logic;
signal s_sm2 : std_logic;
signal s_sm1 : std_logic;
signal s_sm0 : std_logic;
signal s_smod : std_logic;
signal s_int0_h1 : t_ext_l; -- help-bit for edge detection
signal s_int0_h2 : t_ext_l;
signal s_int0_h3 : t_ext_l;
signal s_int1_h1 : t_ext_l;
signal s_int1_h2 : t_ext_l;
signal s_int1_h3 : t_ext_l;
signal s_tf0_h1,s_tf0_h2 : t_tmr_l;
signal s_tf1_h1,s_tf1_h2 : t_tmr_l;
signal s_ri_h1,s_ri_h2 : t_siu_l;
signal s_ti_h1,s_ti_h2 : t_siu_l;
signal s_tsel : muxint;
signal s_ssel : muxint;
signal s_p : std_logic;
signal s_p0 : std_logic_vector(7 downto 0);
signal s_p1 : std_logic_vector(7 downto 0);
signal s_p2 : std_logic_vector(7 downto 0);
signal s_p3 : std_logic_vector(7 downto 0);
signal pc: unsigned(15 downto 0); -- program counter register
signal pc_comb: unsigned(15 downto 0); -- program counter
signal pc_plus1: unsigned(15 downto 0); -- program counter + 1
signal pc_plus2: unsigned(15 downto 0); -- program counter + 2
signal s_data : unsigned(7 downto 0);
signal s_adr : unsigned(7 downto 0);
signal s_preadr : unsigned(7 downto 0);
signal s_bdata : std_logic;
signal s_rr_adr : unsigned (7 downto 0);
signal s_ri_adr : std_logic_vector (7 downto 0);
signal s_ri_data : unsigned (7 downto 0);
-- 8051 standard special-function-register (SFR)
signal p0: unsigned(7 downto 0);
signal sp: unsigned(7 downto 0);
signal dpl: unsigned(7 downto 0);
signal dph: unsigned(7 downto 0);
signal pcon: unsigned(3 downto 0);
signal tcon: t_tmr_lv;
signal tmod: t_tmr_us;
signal p1: unsigned(7 downto 0);
signal scon: t_siu_lv;
signal sbuf: t_siu_us;
signal p2: unsigned(7 downto 0);
signal ie: std_logic_vector(7 downto 0);
signal p3: unsigned(7 downto 0);
signal ip: std_logic_vector(7 downto 0);
signal psw: std_logic_vector(7 downto 0);
signal acc: unsigned(7 downto 0);
signal b: unsigned(7 downto 0);
-- 8051 extended special-function-register
signal tsel: unsigned(7 downto 0); -- select a Timer-Unit
signal ssel: unsigned(7 downto 0); -- select a SIU-Unit
alias CY : std_logic is psw(7);
alias AC : std_logic is psw(6);
alias OV : std_logic is psw(2);
alias EA: std_logic is ie(7);
alias ES: std_logic is ie(4);
alias ET1: std_logic is ie(3);
alias EX1: std_logic is ie(2);
alias ET0: std_logic is ie(1);
alias EX0: std_logic is ie(0);
alias PS0: std_logic is ip(4);
alias PT1: std_logic is ip(3);
alias PX1: std_logic is ip(2);
alias PT0: std_logic is ip(1);
alias PX0: std_logic is ip(0);
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