?? control_fsm.vhd
字號:
-------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.mc8051_p.all;
------------------------ ENTITY DECLARATION -------------------------
entity control_fsm is
port (state_i : in t_state; -- actual state
help_i : in std_logic_vector (7 downto 0); -- general help-reg
bit_data_i : in std_logic; -- bitdata from regs
aludata_i : in std_logic_vector (7 downto 0); -- ALU result
command_i : in std_logic_vector (7 downto 0); -- actual command
inthigh_i : in std_logic; -- high priority int is running
intlow_i : in std_logic; -- low priority int is running
intpre_i : in std_logic; -- an interrupt must start
intpre2_i : in std_logic; -- prepare for interrupt
intblock_i : in std_logic; -- interrupt delay at RETI, IE, IP
ti_i : in std_logic;
ri_i : in std_logic;
ie0_i : in std_logic;
ie1_i : in std_logic;
tf0_i : in std_logic;
tf1_i : in std_logic;
acc : in std_logic_vector(7 downto 0);
psw : in std_logic_vector(7 downto 0);
ie : in std_logic_vector(7 downto 0);
ip : in std_logic_vector(7 downto 0);
alu_cmd_o : out std_logic_vector (5 downto 0); -- ALU code
pc_inc_en_o : out std_logic_vector (3 downto 0);
nextstate_o : out t_state; -- enable signal for state
adr_mux_o : out std_logic_vector (3 downto 0);
adrx_mux_o : out std_logic_vector (1 downto 0);
wrx_mux_o : out std_logic;
data_mux_o : out std_logic_vector (3 downto 0);
bdata_mux_o : out std_logic_vector (3 downto 0);
regs_wr_en_o : out std_logic_vector (2 downto 0);
help_en_o : out std_logic_vector (3 downto 0);
help16_en_o : out std_logic_vector (1 downto 0);
helpb_en_o : out std_logic;
inthigh_en_o : out std_logic;
intlow_en_o : out std_logic;
intpre2_en_o : out std_logic;
inthigh_d_o : out std_logic;
intlow_d_o : out std_logic;
intpre2_d_o : out std_logic;
ext0isr_d_o : out std_logic;
ext1isr_d_o : out std_logic;
ext0isrh_d_o : out std_logic;
ext1isrh_d_o : out std_logic;
ext0isr_en_o : out std_logic;
ext1isr_en_o : out std_logic;
ext0isrh_en_o : out std_logic;
ext1isrh_en_o : out std_logic);
end control_fsm;
-------------------------------------------------------------------------------
architecture rtl of control_fsm is
alias CY : std_logic is psw(7); -- carry
alias AC : std_logic is psw(6); -- auxilary carry
alias OV : std_logic is psw(2); -- overflow flag
alias EA: std_logic is ie(7); -- enable interupts
alias ES: std_logic is ie(4); -- enable serial interupt
alias ET1: std_logic is ie(3); -- enable timer 1 interupt
alias EX1: std_logic is ie(2); -- enable external 1 interupt
alias ET0: std_logic is ie(1); -- enable timer 0 interupt
alias EX0: std_logic is ie(0); -- enable external 0 interupt
alias PS0: std_logic is ip(4); -- priority of serial interupt
alias PT1: std_logic is ip(3); -- priority of timer1 interupt
alias PX1: std_logic is ip(2); -- priority of ext1 interupt
alias PT0: std_logic is ip(1); -- priority of timer0 interupt
alias PX0: std_logic is ip(0); -- priority of ext0 interupt
signal state: t_state; -- actual state
signal s_nextstate: t_state; -- enable signal for state
signal s_instr_category : t_instr_category; -- predecoded insturction
signal s_help: unsigned (7 downto 0); -- general help-register
signal s_bit_data : std_logic; -- bitdata from MUX
signal s_intpre: std_logic; -- an interrupt must start
signal s_intpre2: std_logic; -- prepare for interrupt
signal s_inthigh: std_logic; -- high priority int is running
signal s_intlow: std_logic; -- low priority int is running
signal s_tf1 : std_logic; -- Timer1-Overflowflag
signal s_tf0 : std_logic; -- Timer0-Overflowflag
signal s_ie1 : std_logic; -- ExtINT1-Flag
signal s_ie0 : std_logic; -- ExtINT0-Flag
signal s_ri : std_logic; -- serial receive-ready
signal s_ti : std_logic; -- serial transmit-ready
signal s_command: std_logic_vector (7 downto 0); -- actual command
signal s_pc_inc_en : std_logic_vector (3 downto 0); -- pc control
signal s_regs_wr_en : std_logic_vector (2 downto 0); -- write control
signal s_data_mux : std_logic_vector (3 downto 0); -- data control
signal s_bdata_mux : std_logic_vector (3 downto 0); -- bitdata control
signal s_adr_mux : std_logic_vector (3 downto 0); -- adress control
signal s_adrx_mux : std_logic_vector (1 downto 0); -- ext. adress control
signal s_wrx_mux : std_logic; -- ext. write control
signal s_help_en : std_logic_vector (3 downto 0); -- helpreg control
signal s_help16_en : std_logic_vector (1 downto 0); -- help16 control
signal s_helpb_en : std_logic; -- helpbit control
signal s_intpre2_d : std_logic; -- intput of intpre2
signal s_intpre2_en : std_logic; -- control
signal s_intlow_d : std_logic; -- input of intlow
signal s_intlow_en : std_logic; -- control
signal s_inthigh_d : std_logic; -- input of inthigh
signal s_inthigh_en : std_logic; -- control
signal s_ext0isr_d : std_logic; -- ext int 0 ISR running if set
signal s_ext1isr_d : std_logic; -- ext int 1 ISR running if set
signal s_ext0isrh_d : std_logic; -- ext int 0 ISR has high priority if 1
signal s_ext1isrh_d : std_logic; -- ext int 1 ISR has high priority if 1
signal s_ext0isr_en : std_logic;
signal s_ext1isr_en : std_logic;
signal s_ext0isrh_en : std_logic;
signal s_ext1isrh_en : std_logic;
begin
-- some simple signal-assignments for outputs
pc_inc_en_o <= s_pc_inc_en;
nextstate_o <= s_nextstate;
adr_mux_o <= s_adr_mux;
adrx_mux_o <= s_adrx_mux;
wrx_mux_o <= s_wrx_mux;
data_mux_o <= s_data_mux;
bdata_mux_o <= s_bdata_mux;
regs_wr_en_o <= s_regs_wr_en;
help_en_o <= s_help_en;
help16_en_o <= s_help16_en;
helpb_en_o <= s_helpb_en;
inthigh_en_o <= s_inthigh_en;
intlow_en_o <= s_intlow_en;
intpre2_en_o <= s_intpre2_en;
inthigh_d_o <= s_inthigh_d;
intlow_d_o <= s_intlow_d;
intpre2_d_o <= s_intpre2_d;
ext0isr_d_o <= s_ext0isr_d;
ext1isr_d_o <= s_ext1isr_d;
ext0isrh_d_o <= s_ext0isrh_d;
ext1isrh_d_o <= s_ext1isrh_d;
ext0isr_en_o <= s_ext0isr_en;
ext1isr_en_o <= s_ext1isr_en;
ext0isrh_en_o <= s_ext0isrh_en;
ext1isrh_en_o <= s_ext1isrh_en;
-- some simple signal assignments from intputs
state <= state_i;
s_help <= unsigned(help_i);
s_bit_data <= bit_data_i;
s_command <= command_i;
s_inthigh <= inthigh_i;
s_intlow <= intlow_i;
s_intpre <= intpre_i;
s_intpre2 <= intpre2_i;
s_ti <= ti_i;
s_ri <= ri_i;
s_ie0 <= ie0_i;
s_ie1 <= ie1_i;
s_tf0 <= tf0_i;
s_tf1 <= tf1_i;
-- predecode instruction
s_instr_category <=
IC_ACALL when s_command(4 downto 0) = ACALL else
IC_ADD_A_RR when s_command(7 downto 3) = ADD_A_RR else
IC_ADD_A_D when s_command = ADD_A_D else
IC_ADD_A_ATRI when s_command(7 downto 1) = ADD_A_ATRI else
IC_ADD_A_DATA when s_command = ADD_A_DATA else
IC_ADDC_A_RR when s_command(7 downto 3) = ADDC_A_RR else
IC_ADDC_A_D when s_command = ADDC_A_D else
IC_ADDC_A_ATRI when s_command(7 downto 1) = ADDC_A_ATRI else
IC_ADDC_A_DATA when s_command = ADDC_A_DATA else
IC_AJMP when s_command(4 downto 0) = AJMP else
IC_ANL_A_RR when s_command(7 downto 3) = ANL_A_RR else
IC_ANL_A_D when s_command = ANL_A_D else
IC_ANL_A_ATRI when s_command(7 downto 1) = ANL_A_ATRI else
IC_ANL_A_DATA when s_command = ANL_A_DATA else
IC_ANL_D_A when s_command = ANL_D_A else
IC_ANL_D_DATA when s_command = ANL_D_DATA else
IC_ANL_C_BIT when s_command = ANL_C_BIT else
IC_ANL_C_NBIT when s_command = ANL_C_NBIT else
IC_CJNE_A_D when s_command = CJNE_A_D else
IC_CJNE_A_DATA when s_command = CJNE_A_DATA else
IC_CJNE_RR_DATA when s_command(7 downto 3) = CJNE_RR_DATA else
IC_CJNE_ATRI_DATA when s_command(7 downto 1) = CJNE_ATRI_DATA else
IC_CLR_A when s_command = CLR_A else
IC_CLR_C when s_command = CLR_C else
IC_CLR_BIT when s_command = CLR_BIT else
IC_CPL_A when s_command = CPL_A else
IC_CPL_C when s_command = CPL_C else
IC_CPL_BIT when s_command = CPL_BIT else
IC_DA_A when s_command = DA_A else
IC_DEC_A when s_command = DEC_A else
IC_DEC_RR when s_command(7 downto 3) = DEC_RR else
IC_DEC_D when s_command = DEC_D else
IC_DEC_ATRI when s_command(7 downto 1) = DEC_ATRI else
IC_DIV_AB when s_command = DIV_AB else
IC_DJNZ_RR when s_command(7 downto 3) = DJNZ_RR else
IC_DJNZ_D when s_command = DJNZ_D else
IC_INC_A when s_command = INC_A else
IC_INC_RR when s_command(7 downto 3) = INC_RR else
IC_INC_D when s_command = INC_D else
IC_INC_ATRI when s_command(7 downto 1) = INC_ATRI else
IC_INC_DPTR when s_command = INC_DPTR else
IC_JB when s_command = JB else
IC_JBC when s_command = JBC else
IC_JC when s_command = JC else
IC_JMP_A_DPTR when s_command = JMP_A_DPTR else
IC_JNB when s_command = JNB else
IC_JNC when s_command = JNC else
IC_JNZ when s_command = JNZ else
IC_JZ when s_command = JZ else
IC_LCALL when s_command = LCALL else
IC_LJMP when s_command = LJMP else
IC_MOV_A_RR when s_command(7 downto 3) = MOV_A_RR else
IC_MOV_A_D when s_command = MOV_A_D else
IC_MOV_A_ATRI when s_command(7 downto 1) = MOV_A_ATRI else
IC_MOV_A_DATA when s_command = MOV_A_DATA else
IC_MOV_RR_A when s_command(7 downto 3) = MOV_RR_A else
IC_MOV_RR_D when s_command(7 downto 3) = MOV_RR_D else
IC_MOV_RR_DATA when s_command(7 downto 3) = MOV_RR_DATA else
IC_MOV_D_A when s_command = MOV_D_A else
IC_MOV_D_RR when s_command(7 downto 3) = MOV_D_RR else
IC_MOV_D_D when s_command = MOV_D_D else
IC_MOV_D_ATRI when s_command(7 downto 1) = MOV_D_ATRI else
IC_MOV_D_DATA when s_command = MOV_D_DATA else
IC_MOV_ATRI_A when s_command(7 downto 1) = MOV_ATRI_A else
IC_MOV_ATRI_D when s_command(7 downto 1) = MOV_ATRI_D else
IC_MOV_ATRI_DATA when s_command(7 downto 1) = MOV_ATRI_DATA else
IC_MOVC_A_ATDPTR when s_command = MOVC_A_ATDPTR else
IC_MOVC_A_ATPC when s_command = MOVC_A_ATPC else
IC_MOVX_A_ATRI when s_command(7 downto 1) = MOVX_A_ATRI else
IC_MOVX_A_ATDPTR when s_command = MOVX_A_ATDPTR else
IC_MOVX_ATRI_A when s_command(7 downto 1) = MOVX_ATRI_A else
IC_MOVX_ATDPTR_A when s_command = MOVX_ATDPTR_A else
IC_MOV_C_BIT when s_command = MOV_C_BIT else
IC_MOV_BIT_C when s_command = MOV_BIT_C else
IC_MOV_DPTR_DATA when s_command = MOV_DPTR_DATA else
IC_MUL_AB when s_command = MUL_AB else
IC_NOP when s_command = NOP else
IC_ORL_A_RR when s_command(7 downto 3) = ORL_A_RR else
IC_ORL_A_D when s_command = ORL_A_D else
IC_ORL_A_ATRI when s_command(7 downto 1) = ORL_A_ATRI else
IC_ORL_A_DATA when s_command = ORL_A_DATA else
IC_ORL_D_A when s_command = ORL_D_A else
IC_ORL_D_DATA when s_command = ORL_D_DATA else
IC_ORL_C_BIT when s_command = ORL_C_BIT else
IC_ORL_C_NBIT when s_command = ORL_C_NBIT else
IC_POP when s_command = POP else
IC_PUSH when s_command = PUSH else
IC_RET when s_command = RET else
IC_RETI when s_command = RETI else
IC_RL_A when s_command = RL_A else
IC_RLC_A when s_command = RLC_A else
IC_RR_A when s_command = RR_A else
IC_RRC_A when s_command = RRC_A else
IC_SETB_C when s_command = SETB_C else
IC_SETB_BIT when s_command = SETB_BIT else
IC_SJMP when s_command = SJMP else
IC_SUBB_A_RR when s_command(7 downto 3) = SUBB_A_RR else
IC_SUBB_A_D when s_command = SUBB_A_D else
IC_SUBB_A_ATRI when s_command(7 downto 1) = SUBB_A_ATRI else
IC_SUBB_A_DATA when s_command = SUBB_A_DATA else
IC_SWAP_A when s_command = SWAP_A else
IC_XCH_A_RR when s_command(7 downto 3) = XCH_A_RR else
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