?? mc8051_p.vhd
字號:
intpre2_d_o : out std_logic;
ext0isr_d_o : out std_logic;
ext1isr_d_o : out std_logic;
ext0isrh_d_o : out std_logic;
ext1isrh_d_o : out std_logic;
ext0isr_en_o : out std_logic;
ext1isr_en_o : out std_logic;
ext0isrh_en_o : out std_logic;
ext1isrh_en_o : out std_logic);
end component;
component control_mem
port (pc_o : out std_logic_vector(15 downto 0);
rom_data_i : in std_logic_vector(7 downto 0);
ram_data_o : out std_logic_vector(7 downto 0);
ram_data_i : in std_logic_vector(7 downto 0);
ram_adr_o : out std_logic_vector(6 downto 0);
reg_data_o : out std_logic_vector(7 downto 0);
ram_wr_o : out std_logic;
cy_o : out std_logic_vector(1 downto 0);
ov_o : out std_logic;
ram_en_o : out std_logic;
aludata_i : in std_logic_vector (7 downto 0);
aludatb_i : in std_logic_vector (7 downto 0);
acc_o : out std_logic_vector (7 downto 0);
new_cy_i : in std_logic_vector(1 downto 0);
new_ov_i : in std_logic;
reset : in std_logic;
clk : in std_logic;
int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0);
int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0);
p0_i : in std_logic_vector(7 downto 0);
p1_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0);
p3_i : in std_logic_vector(7 downto 0);
p0_o : out std_logic_vector(7 downto 0);
p1_o : out std_logic_vector(7 downto 0);
p2_o : out std_logic_vector(7 downto 0);
p3_o : out std_logic_vector(7 downto 0);
all_trans_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
all_scon_o : out std_logic_vector(6*C_IMPL_N_SIU-1 downto 0);
all_sbuf_o : out std_logic_vector(8*C_IMPL_N_SIU-1 downto 0);
all_smod_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
all_scon_i : in std_logic_vector(3*C_IMPL_N_SIU-1 downto 0);
all_sbuf_i : in std_logic_vector(8*C_IMPL_N_SIU-1 downto 0);
all_tcon_tr0_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tcon_tr1_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tmod_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_reload_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_wt_o : out std_logic_vector(2*C_IMPL_N_TMR-1 downto 0);
all_wt_en_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tf0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tf1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tl0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_tl1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_th0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_th1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
state_o : out t_state;
help_o : out std_logic_vector(7 downto 0);
bit_data_o : out std_logic;
command_o : out std_logic_vector (7 downto 0);
inthigh_o : out std_logic;
intlow_o : out std_logic;
intpre_o : out std_logic;
intpre2_o : out std_logic;
intblock_o : out std_logic;
ti_o : out std_logic;
ri_o : out std_logic;
ie0_o : out std_logic;
ie1_o : out std_logic;
tf0_o : out std_logic;
tf1_o : out std_logic;
psw_o : out std_logic_vector(7 downto 0);
ie_o : out std_logic_vector(7 downto 0);
ip_o : out std_logic_vector(7 downto 0);
adrx_o : out std_logic_vector(15 downto 0);
datax_o : out std_logic_vector(7 downto 0);
wrx_o : out std_logic;
datax_i : in std_logic_vector(7 downto 0);
pc_inc_en_i : in std_logic_vector (3 downto 0);
nextstate_i : in t_state;
adr_mux_i : in std_logic_vector (3 downto 0);
adrx_mux_i : in std_logic_vector (1 downto 0);
wrx_mux_i : in std_logic;
data_mux_i : in std_logic_vector (3 downto 0);
bdata_mux_i : in std_logic_vector (3 downto 0);
regs_wr_en_i : in std_logic_vector (2 downto 0);
help_en_i : in std_logic_vector (3 downto 0);
help16_en_i : in std_logic_vector (1 downto 0);
helpb_en_i : in std_logic;
inthigh_en_i : in std_logic;
intlow_en_i : in std_logic;
intpre2_en_i : in std_logic;
inthigh_d_i : in std_logic;
intlow_d_i : in std_logic;
intpre2_d_i : in std_logic;
ext0isr_d_i : in std_logic;
ext1isr_d_i : in std_logic;
ext0isrh_d_i : in std_logic;
ext1isrh_d_i : in std_logic;
ext0isr_en_i : in std_logic;
ext1isr_en_i : in std_logic;
ext0isrh_en_i : in std_logic;
ext1isrh_en_i : in std_logic);
end component;
component mc8051_control
port (pc_o : out std_logic_vector(15 downto 0);
rom_data_i : in std_logic_vector(7 downto 0);
ram_data_o : out std_logic_vector(7 downto 0);
ram_data_i : in std_logic_vector(7 downto 0);
ram_adr_o : out std_logic_vector(6 downto 0);
reg_data_o : out std_logic_vector(7 downto 0);
ram_wr_o : out std_logic;
cy_o : out std_logic_vector(1 downto 0);
ov_o : out std_logic;
ram_en_o : out std_logic;
alu_cmd_o : out std_logic_vector (5 downto 0);
aludata_i : in std_logic_vector (7 downto 0);
aludatb_i : in std_logic_vector (7 downto 0);
acc_o : out std_logic_vector (7 downto 0);
new_cy_i : in std_logic_vector(1 downto 0);
new_ov_i : in std_logic;
reset : in std_logic;
clk : in std_logic;
int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0);
int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0);
datax_i : in std_logic_vector (7 downto 0);
datax_o : out std_logic_vector (7 downto 0);
adrx_o : out std_logic_vector (15 downto 0);
wrx_o : out std_logic;
p0_i : in std_logic_vector(7 downto 0);
p1_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0);
p3_i : in std_logic_vector(7 downto 0);
p0_o : out std_logic_vector(7 downto 0);
p1_o : out std_logic_vector(7 downto 0);
p2_o : out std_logic_vector(7 downto 0);
p3_o : out std_logic_vector(7 downto 0);
all_trans_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
all_scon_o : out std_logic_vector(6*C_IMPL_N_SIU-1 downto 0);
all_sbuf_o : out std_logic_vector(8*C_IMPL_N_SIU-1 downto 0);
all_smod_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
all_scon_i : in std_logic_vector(3*C_IMPL_N_SIU-1 downto 0);
all_sbuf_i : in std_logic_vector(8*C_IMPL_N_SIU-1 downto 0);
all_tcon_tr0_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tcon_tr1_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tmod_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_reload_o : out std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_wt_o : out std_logic_vector(2*C_IMPL_N_TMR-1 downto 0);
all_wt_en_o : out std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tf0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tf1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_tl0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_tl1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_th0_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0);
all_th1_i : in std_logic_vector(8*C_IMPL_N_TMR-1 downto 0));
end component;
component mc8051_core
port (clk : in std_logic;
reset : in std_logic;
rom_data_i : in std_logic_vector(7 downto 0);
ram_data_i : in std_logic_vector(7 downto 0);
int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0);
int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0);
all_t0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_t1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_rxd_i : in std_logic_vector(C_IMPL_N_SIU-1 downto 0);
p0_i : in std_logic_vector(7 downto 0);
p1_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0);
p3_i : in std_logic_vector(7 downto 0);
p0_o : out std_logic_vector(7 downto 0);
p1_o : out std_logic_vector(7 downto 0);
p2_o : out std_logic_vector(7 downto 0);
p3_o : out std_logic_vector(7 downto 0);
all_rxd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
all_txd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
all_rxdwr_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
rom_adr_o : out std_logic_vector(15 downto 0);
ram_data_o : out std_logic_vector(7 downto 0);
ram_adr_o : out std_logic_vector(6 downto 0);
ram_wr_o : out std_logic;
ram_en_o : out std_logic;
datax_i : in std_logic_vector (7 downto 0);
datax_o : out std_logic_vector (7 downto 0);
adrx_o : out std_logic_vector (15 downto 0);
wrx_o : out std_logic);
end component;
component mc8051_top
port (clk : in std_logic;
reset : in std_logic;
int0_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0);
int1_i : in std_logic_vector(C_IMPL_N_EXT-1 downto 0);
all_t0_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_t1_i : in std_logic_vector(C_IMPL_N_TMR-1 downto 0);
all_rxd_i : in std_logic_vector(C_IMPL_N_SIU-1 downto 0);
p0_i : in std_logic_vector(7 downto 0);
p1_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0);
p3_i : in std_logic_vector(7 downto 0);
p0_o : out std_logic_vector(7 downto 0);
p1_o : out std_logic_vector(7 downto 0);
p2_o : out std_logic_vector(7 downto 0);
p3_o : out std_logic_vector(7 downto 0);
all_rxd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
all_txd_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0);
all_rxdwr_o : out std_logic_vector(C_IMPL_N_SIU-1 downto 0));
end component;
-----------------------------------------------------------------------------
-- START: Component declarations for simulation models
-----------------------------------------------------------------------------
component mc8051_ram
port (clk : in std_logic;
--reset : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
addr : in std_logic_vector(6 downto 0);
we : in std_logic;
en : in std_logic);
end component;
-- component mc8051_ramx
-- port (clk : in std_logic;
-- reset : in std_logic;
-- ram_data_i : in std_logic_vector(7 downto 0);
-- ram_data_o : out std_logic_vector(7 downto 0);
-- ram_adr_i : in std_logic_vector(15 downto 0);
-- ram_wr_i : in std_logic);
-- end component;
component mc8051_rom
port (clk : in std_logic;
--reset : in std_logic;
dout : out std_logic_vector(7 downto 0);
addr : in std_logic_vector(9 downto 0));
end component;
component mc8051_clockdiv
port (clk : in std_logic;
clkdiv : out std_logic);
end component;
-----------------------------------------------------------------------------
-- END: Component declarations for simulation models
-----------------------------------------------------------------------------
end mc8051_p;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -