?? comb_mltplr.vhd
字號:
-- Description: Multiplier with parameteriseable data width. Realised
-- using combinational logic only.
--
--
--
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--------------------------------ENTITY DECLARATION----------------------------------------
entity comb_mltplr is
generic (DWIDTH : integer := 8);
port (mltplcnd_i : in std_logic_vector(DWIDTH-1 downto 0); -- Multiplicand
mltplctr_i : in std_logic_vector(DWIDTH-1 downto 0); -- Multiplicator
product_o : out std_logic_vector((DWIDTH*2)-1 downto 0)); -- Product
end comb_mltplr;
----------------------------------------------------------------------------------------
architecture rtl of comb_mltplr is
begin -- rtl
-- purpose: Multiply the multiplicand with the multiplicator.
-- type : combinational
-- inputs : dvdnd_i, dvsor_i
-- outputs: product_o
p_mltply: process (mltplctr_i, mltplcnd_i)
variable v_product : unsigned(DWIDTH*2-1 downto 0);
begin -- process p_divide
v_product := conv_unsigned(unsigned(mltplctr_i)
* unsigned(mltplcnd_i),DWIDTH*2);
product_o <= std_logic_vector(v_product);
end process p_mltply;
end rtl;
-------------------------------------------------------------------------------
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