?? mc8051_tmrctr.vhd
字號:
-------------------------------------------------------------------------------
when "10" =>
-- This section generates the timer/counter overflow flag0
if s_tmr_ctr0_en = '1' then
if s_count_enable = '1' then
if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then
if s_count0(7 downto 0) = conv_unsigned(255,16) then
s_tf0 <= '1';
else
s_tf0 <= '0';
end if;
end if;
end if;
end if;
-- This section generates the low byte register of tmr/ctr0
if wt_i = "00" and wt_en_i = '1' then
s_countl0 <= unsigned(reload_i);
else
if s_tmr_ctr0_en = '1' then
if s_count_enable = '1' then
if s_c_t0 = '0' then
if s_countl0 = conv_unsigned(255,8) then
s_countl0 <= s_counth0;
else
s_countl0 <= s_countl0 + conv_unsigned(1,1);
end if;
else
if s_ext_edge0 = '1' then
if s_countl0 = conv_unsigned(255,8) then
s_countl0 <= s_counth0;
else
s_countl0 <= s_countl0 + conv_unsigned(1,1);
end if;
end if;
end if;
end if;
end if;
end if;
-- This section generates the high byte register of tmr/ctr0
if wt_i = "10" and wt_en_i = '1' then
s_counth0 <= unsigned(reload_i);
end if;
-------------------------------------------------------------------------------
-- operating mode 3 (One 8 bit timer/counter and one 8 bit timer)
-------------------------------------------------------------------------------
when "11" =>
-- This section generates the timer/counter overflow flag0
if s_tmr_ctr0_en = '1' then
if s_count_enable = '1' then
if s_c_t0 = '0' or (s_ext_edge0 = '1' and s_c_t0 = '1') then
if s_count0(7 downto 0) = conv_unsigned(255,16) then
s_tf0 <= '1';
else
s_tf0 <= '0';
end if;
end if;
end if;
end if;
-- This section generates the low byte register of tmr/ctr0
if wt_i = "00" and wt_en_i = '1' then
s_countl0 <= unsigned(reload_i);
else
if s_tmr_ctr0_en = '1' then
if s_count_enable = '1' then
if s_c_t0 = '0' then
if s_countl0 = conv_unsigned(255,8) then
s_countl0 <= conv_unsigned(0,8);
else
s_countl0 <= s_countl0 + conv_unsigned(1,1);
end if;
else
if s_ext_edge0 = '1' then
if s_countl0 = conv_unsigned(255,8) then
s_countl0 <= conv_unsigned(0,8);
else
s_countl0 <= s_countl0 + conv_unsigned(1,1);
end if;
end if;
end if;
end if;
end if;
end if;
-- This section generates the timer/counter overflow flag1
if tcon_tr1_i = '1' then
if s_count_enable = '1' then
if s_count0(15 downto 8) = conv_unsigned(255,8) then
s_tf1 <= '1';
else
s_tf1 <= '0';
end if;
end if;
end if;
-- This section generates the high byte register of tmr/ctr0
if wt_i = "10" and wt_en_i = '1' then
s_counth0 <= unsigned(reload_i);
else
if tcon_tr1_i = '1' then
if s_count_enable = '1' then
if s_counth0 = conv_unsigned(255,8) then
s_counth0 <= conv_unsigned(0,8);
else
s_counth0 <= s_counth0 + conv_unsigned(1,1);
end if;
end if;
end if;
end if;
when others => null;
end case;
------------------------------------------------------------------------------
--+++++++++++++++++ END OF TIMER / COUNTER 0 +++++++++++++++++++++++++++--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--+++++++++++++++++++++ TIMER / COUNTER 1 ++++++++++++++++++++++++++++++--
------------------------------------------------------------------------------
-- This is timer/counter1. It is built around the 16 bit count register
-- s_count1 and realises its four operating modes
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- operating mode 0 (13 bit timer/counter)
-------------------------------------------------------------------------------
case s_mode1 is
when "00" =>
-- This section generates the timer/counter overflow flag1
if s_tmr_ctr1_en = '1' then
if s_count_enable = '1' then
if s_mode0 = conv_unsigned(1,2) or
s_mode0 = conv_unsigned(0,2) or
s_mode0 = conv_unsigned(2,2) then
if s_c_t1 = '0' or (s_ext_edge1 = '1' and s_c_t1 = '1') then
if s_count1 = conv_unsigned(65311,16) then -- ***
s_tf1 <= '1';
else
s_tf1 <= '0';
end if;
end if;
else
null;
end if;
end if;
end if;
-- This section generates the low byte register of tmr/ctr1
if wt_i = "01" and wt_en_i = '1' then
s_countl1 <= unsigned(reload_i);
else
if s_tmr_ctr1_en = '1' then
if s_count_enable = '1' then
if s_c_t1 = '0' then
if s_countl1 = conv_unsigned(31,8) then -- ***
s_countl1 <= conv_unsigned(0,8);
else
s_countl1 <= s_countl1 + conv_unsigned(1,1);
end if;
else
if s_ext_edge1 = '1' then
if s_countl1 = conv_unsigned(31,8) then -- ***
s_countl1 <= conv_unsigned(0,8);
else
s_countl1 <= s_countl1 + conv_unsigned(1,1);
end if;
end if;
end if;
end if;
end if;
end if;
-- This section generates the high byte register of tmr/ctr1
if wt_i = "11" and wt_en_i = '1' then
s_counth1 <= unsigned(reload_i);
else
if s_tmr_ctr1_en = '1' then
if s_count_enable = '1' then
if s_c_t1 = '0' then
if s_count1 = conv_unsigned(65311,16) then -- ***
s_counth1 <= conv_unsigned(0,8);
else
if s_countl1 = conv_unsigned(31,8) then -- ***
s_counth1 <= s_counth1 + conv_unsigned(1,1);
end if;
end if;
else
if s_ext_edge1 = '1' then
if s_count1 = conv_unsigned(65311,16) then -- ***
s_counth1 <= conv_unsigned(0,8);
else
if s_countl1 = conv_unsigned(31,8) then -- ***
s_counth1 <= s_counth1 + conv_unsigned(1,1);
end if;
end if;
end if;
end if;
end if;
end if;
end if;
-------------------------------------------------------------------------------
-- operating mode 1 (16 bit timer/counter)
-------------------------------------------------------------------------------
when "01" =>
-- This section generates the timer/counter overflow flag1
if s_tmr_ctr1_en = '1' then
if s_count_enable = '1' then
if s_mode0 = conv_unsigned(1,2) or
s_mode0 = conv_unsigned(0,2) or
s_mode0 = conv_unsigned(2,2) then
if s_c_t1 = '0' or (s_ext_edge1 = '1' and s_c_t1 = '1') then
if s_count1 = conv_unsigned(65535,16) then
s_tf1 <= '1';
else
s_tf1 <= '0';
end if;
end if;
else
null;
end if;
end if;
end if;
-- This section generates the low byte register of tmr/ctr1
if wt_i = "01" and wt_en_i = '1' then
s_countl1 <= unsigned(reload_i);
else
if s_tmr_ctr1_en = '1' then
if s_count_enable = '1' then
if s_c_t1 = '0' then
if s_count1 = conv_unsigned(65535,16) then
s_countl1 <= conv_unsigned(0,8);
else
s_countl1 <= s_countl1 + conv_unsigned(1,1);
end if;
else
if s_ext_edge1 = '1' then
if s_count1 = conv_unsigned(65535,16) then
s_countl1 <= conv_unsigned(0,8);
else
s_countl1 <= s_countl1 + conv_unsigned(1,1);
end if;
end if;
end if;
end if;
end if;
end if;
-- This section generates the high byte register of tmr/ctr1
if wt_i = "11" and wt_en_i = '1' then
s_counth1 <= unsigned(reload_i);
else
if s_tmr_ctr1_en = '1' then
if s_count_enable = '1' then
if s_c_t1 = '0' then
if s_count1 = conv_unsigned(65535,16) then
s_counth1 <= conv_unsigned(0,8);
else
if s_countl1 = conv_unsigned(255,8) then
s_counth1 <= s_counth1 + conv_unsigned(1,1);
end if;
end if;
else
if s_ext_edge1 = '1' then
if s_count1 = conv_unsigned(65535,16) then
s_counth1 <= conv_unsigned(0,8);
else
if s_countl1 = conv_unsigned(255,8) then
s_counth1 <= s_counth1 + conv_unsigned(1,1);
end if;
end if;
end if;
end if;
end if;
end if;
end if;
-------------------------------------------------------------------------------
-- operating mode 2 (8 bit timer/counter, auto reloaded)
-------------------------------------------------------------------------------
when "10" =>
-- This section generates the timer/counter overflow flag1
if s_tmr_ctr1_en = '1' then
if s_count_enable = '1' then
if s_mode0 = conv_unsigned(1,2) or
s_mode0 = conv_unsigned(0,2) or
s_mode0 = conv_unsigned(2,2) then
if s_c_t1 = '0' or (s_ext_edge1 = '1' and s_c_t1 = '1') then
if s_count1(7 downto 0) = conv_unsigned(255,16) then
s_tf1 <= '1';
else
s_tf1 <= '0';
end if;
end if;
else
null;
end if;
end if;
end if;
-- This section generates the low byte register of tmr/ctr1
if wt_i = "01" and wt_en_i = '1' then
s_countl1 <= unsigned(reload_i);
else
if s_tmr_ctr1_en = '1' then
if s_count_enable = '1' then
if s_c_t1 = '0' then
if s_countl1 = conv_unsigned(255,8) then
s_countl1 <= s_counth1;
else
s_countl1 <= s_countl1 + conv_unsigned(1,1);
end if;
else
if s_ext_edge1 = '1' then
if s_countl1 = conv_unsigned(255,8) then
s_countl1 <= s_counth1;
else
s_countl1 <= s_countl1 + conv_unsigned(1,1);
end if;
end if;
end if;
end if;
end if;
end if;
-- This section generates the high byte register of tmr/ctr1
if wt_i = "11" and wt_en_i = '1' then
s_counth1 <= unsigned(reload_i);
end if;
-------------------------------------------------------------------------------
-- operating mode 3 (One 8 bit timer/counter and one 8 bit timer)
-------------------------------------------------------------------------------
when "11" =>
-- This section generates the low byte register of tmr/ctr1
if wt_i = "01" and wt_en_i = '1' then
s_countl1 <= unsigned(reload_i);
end if;
-- This section generates the high byte register of tmr/ctr1
if wt_i = "11" and wt_en_i = '1' then
s_counth1 <= unsigned(reload_i);
end if;
when others => null;
end case;
------------------------------------------------------------------------------
--+++++++++++++++++ END OF TIMER / COUNTER 1 +++++++++++++++++++++++++++--
------------------------------------------------------------------------------
end if;
end if;
end process p_tmr_ctr;
end rtl;
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