?? dsp28_mcbsp.h
字號(hào):
struct XCERE_BITS bit;
};
// XCERF control register bit definitions:
struct XCERF_BITS { // bit description
Uint16 XCEF0:1; // 0 Receive Channel enable bit
Uint16 XCEF1:1; // 1 Receive Channel enable bit
Uint16 XCEF2:1; // 2 Receive Channel enable bit
Uint16 XCEF3:1; // 3 Receive Channel enable bit
Uint16 XCEF4:1; // 4 Receive Channel enable bit
Uint16 XCEF5:1; // 5 Receive Channel enable bit
Uint16 XCEF6:1; // 6 Receive Channel enable bit
Uint16 XCEF7:1; // 7 Receive Channel enable bit
Uint16 XCEF8:1; // 8 Receive Channel enable bit
Uint16 XCEF9:1; // 9 Receive Channel enable bit
Uint16 XCEF10:1; // 10 Receive Channel enable bit
Uint16 XCEF11:1; // 11 Receive Channel enable bit
Uint16 XCEF12:1; // 12 Receive Channel enable bit
Uint16 XCEF13:1; // 13 Receive Channel enable bit
Uint16 XCEF14:1; // 14 Receive Channel enable bit
Uint16 XCEF15:1; // 15 Receive Channel enable bit
};
union XCERF_REG {
Uint16 all;
struct XCERF_BITS bit;
};
// RCERG control register bit definitions:
struct RCERG_BITS { // bit description
Uint16 RCEG0:1; // 0 Receive Channel enable bit
Uint16 RCEG1:1; // 1 Receive Channel enable bit
Uint16 RCEG2:1; // 2 Receive Channel enable bit
Uint16 RCEG3:1; // 3 Receive Channel enable bit
Uint16 RCEG4:1; // 4 Receive Channel enable bit
Uint16 RCEG5:1; // 5 Receive Channel enable bit
Uint16 RCEG6:1; // 6 Receive Channel enable bit
Uint16 RCEG7:1; // 7 Receive Channel enable bit
Uint16 RCEG8:1; // 8 Receive Channel enable bit
Uint16 RCEG9:1; // 9 Receive Channel enable bit
Uint16 RCEG10:1; // 10 Receive Channel enable bit
Uint16 RCEG11:1; // 11 Receive Channel enable bit
Uint16 RCEG12:1; // 12 Receive Channel enable bit
Uint16 RCEG13:1; // 13 Receive Channel enable bit
Uint16 RCEG14:1; // 14 Receive Channel enable bit
Uint16 RCEG15:1; // 15 Receive Channel enable bit
};
union RCERG_REG {
Uint16 all;
struct RCERG_BITS bit;
};
// RCERH control register bit definitions:
struct RCERH_BITS { // bit description
Uint16 RCEH0:1; // 0 Receive Channel enable bit
Uint16 RCEH1:1; // 1 Receive Channel enable bit
Uint16 RCEH2:1; // 2 Receive Channel enable bit
Uint16 RCEH3:1; // 3 Receive Channel enable bit
Uint16 RCEH4:1; // 4 Receive Channel enable bit
Uint16 RCEH5:1; // 5 Receive Channel enable bit
Uint16 RCEH6:1; // 6 Receive Channel enable bit
Uint16 RCEH7:1; // 7 Receive Channel enable bit
Uint16 RCEH8:1; // 8 Receive Channel enable bit
Uint16 RCEH9:1; // 9 Receive Channel enable bit
Uint16 RCEH10:1; // 10 Receive Channel enable bit
Uint16 RCEH11:1; // 11 Receive Channel enable bit
Uint16 RCEH12:1; // 12 Receive Channel enable bit
Uint16 RCEH13:1; // 13 Receive Channel enable bit
Uint16 RCEH14:1; // 14 Receive Channel enable bit
Uint16 RCEH15:1; // 15 Receive Channel enable bit
};
union RCERH_REG {
Uint16 all;
struct RCERH_BITS bit;
};
// XCERG control register bit definitions:
struct XCERG_BITS { // bit description
Uint16 XCEG0:1; // 0 Receive Channel enable bit
Uint16 XCEG1:1; // 1 Receive Channel enable bit
Uint16 XCEG2:1; // 2 Receive Channel enable bit
Uint16 XCEG3:1; // 3 Receive Channel enable bit
Uint16 XCEG4:1; // 4 Receive Channel enable bit
Uint16 XCEG5:1; // 5 Receive Channel enable bit
Uint16 XCEG6:1; // 6 Receive Channel enable bit
Uint16 XCEG7:1; // 7 Receive Channel enable bit
Uint16 XCEG8:1; // 8 Receive Channel enable bit
Uint16 XCEG9:1; // 9 Receive Channel enable bit
Uint16 XCEG10:1; // 10 Receive Channel enable bit
Uint16 XCEG11:1; // 11 Receive Channel enable bit
Uint16 XCEG12:1; // 12 Receive Channel enable bit
Uint16 XCEG13:1; // 13 Receive Channel enable bit
Uint16 XCEG14:1; // 14 Receive Channel enable bit
Uint16 XCEG15:1; // 15 Receive Channel enable bit
};
union XCERG_REG {
Uint16 all;
struct XCERG_BITS bit;
};
// XCERH control register bit definitions:
struct XCERH_BITS { // bit description
Uint16 XCEH0:1; // 0 Receive Channel enable bit
Uint16 XCEH1:1; // 1 Receive Channel enable bit
Uint16 XCEH2:1; // 2 Receive Channel enable bit
Uint16 XCEH3:1; // 3 Receive Channel enable bit
Uint16 XCEH4:1; // 4 Receive Channel enable bit
Uint16 XCEH5:1; // 5 Receive Channel enable bit
Uint16 XCEH6:1; // 6 Receive Channel enable bit
Uint16 XCEH7:1; // 7 Receive Channel enable bit
Uint16 XCEH8:1; // 8 Receive Channel enable bit
Uint16 XCEH9:1; // 9 Receive Channel enable bit
Uint16 XCEH10:1; // 10 Receive Channel enable bit
Uint16 XCEH11:1; // 11 Receive Channel enable bit
Uint16 XCEH12:1; // 12 Receive Channel enable bit
Uint16 XCEH13:1; // 13 Receive Channel enable bit
Uint16 XCEH14:1; // 14 Receive Channel enable bit
Uint16 XCEH15:1; // 15 Receive Channel enable bit
};
union XCERH_REG {
Uint16 all;
struct XCERH_BITS bit;
};
// McBSP FIFO Transmit register bit definitions:
struct MFFTX_BITS { // bit description
Uint16 IL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 INT_CLR:1; // 6 Clear INT flag
Uint16 INT:1; // 7 INT flag
Uint16 ST:5; // 12:8 FIFO status
Uint16 XRESET:1; // 13 FIFO reset
Uint16 MFFENA:1; // 14 Enhancement enable
Uint16 rsvd:1; // 15 reserved
};
union MFFTX_REG {
Uint16 all;
struct MFFTX_BITS bit;
};
// McBSP FIFO recieve register bit definitions:
struct MFFRX_BITS { // bits description
Uint16 IL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 INT_CLR:1; // 6 Clear INT flag
Uint16 INT:1; // 7 INT flag
Uint16 ST:5; // 12:8 FIFO status
Uint16 RRESET:1; // 13 FIFO reset
Uint16 OVF_CLR:1; // 14 Clear overflow
Uint16 OVF:1; // 15 FIFO overflow
};
union MFFRX_REG {
Uint16 all;
struct MFFRX_BITS bit;
};
// McBSP FIFO control register bit definitions:
struct MFFCT_BITS { // bits description
Uint16 TXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:7; // 15:7 reserved
Uint16 IACKM:1; // 15 is IACK mode enable bit
};
union MFFCT_REG {
Uint16 all;
struct MFFCT_BITS bit;
};
// McBSP FIFO INTERRUPT control register bit definitions:
struct MFFINT_BITS { // bits description
Uint16 XINT:1; // 0 XINT interrupt enable
Uint16 XEVTA:1; // 1 XEVTA interrupt enable
Uint16 RINT:1; // 2 RINT interrupt enable
Uint16 REVTA:1; // 3 REVTA interrupt enable
Uint16 rsvd:12; // 15:4 reserved
};
union MFFINT_REG {
Uint16 all;
struct MFFINT_BITS bit;
};
// McBSP FIFO INTERRUPT status register bit definitions:
struct MFFST_BITS { // bits description
Uint16 EOBX:1; // 0 EOBX flag
Uint16 FSX:1; // 1 FSX flag
Uint16 EOBR:1; // 2 EOBR flag
Uint16 FSR:1; // 3 FSR flag
Uint16 rsvd:12; // 15:4 reserved
};
union MFFST_REG {
Uint16 all;
struct MFFST_BITS bit;
};
//---------------------------------------------------------------------------
// McBSP Register File:
//
struct MCBSP_REGS {
union DRR2_REG DRR2; // 0, MCBSP Data receive register bits 31-16
union DRR1_REG DRR1; // 1, MCBSP Data receive register bits 15-0
union DXR2_REG DXR2; // 2, MCBSP Data transmit register bits 31-16
union DXR1_REG DXR1; // 3, MCBSP Data transmit register bits 15-0
union SPCR2_REG SPCR2; // 4, MCBSP control register bits 31-16
union SPCR1_REG SPCR1; // 5, MCBSP control register bits 15-0
union RCR2_REG RCR2; // 6, MCBSP receive control register bits 31-16
union RCR1_REG RCR1; // 7, MCBSP receive control register bits 15-0
union XCR2_REG XCR2; // 8, MCBSP transmit control register bits 31-16
union XCR1_REG XCR1; // 9, MCBSP transmit control register bits 15-0
union SRGR2_REG SRGR2; // 10, MCBSP sample rate gen register bits 31-16
union SRGR1_REG SRGR1; // 11, MCBSP sample rate gen register bits 15-0
union MCR2_REG MCR2; // 12, MCBSP multichannel register bits 31-16
union MCR1_REG MCR1; // 13, MCBSP multichannel register bits 15-0
union RCERA_REG RCERA; // 14, MCBSP Receive channel enable partition A
union RCERB_REG RCERB; // 15, MCBSP Receive channel enable partition B
union XCERA_REG XCERA; // 16, MCBSP Transmit channel enable partition A
union XCERB_REG XCERB; // 17, MCBSP Transmit channel enable partition B
union PCR1_REG PCR1; // 18, MCBSP Pin control register bits 15-0
union RCERC_REG RCERC; // 19, MCBSP Receive channel enable partition C
union RCERD_REG RCERD; // 20, MCBSP Receive channel enable partition D
union XCERC_REG XCERC; // 21, MCBSP Transmit channel enable partition C
union XCERD_REG XCERD; // 23, MCBSP Transmit channel enable partition D
union RCERE_REG RCERE; // 24, MCBSP Receive channel enable partition E
union RCERF_REG RCERF; // 25, MCBSP Receive channel enable partition F
union XCERE_REG XCERE; // 26, MCBSP Transmit channel enable partition E
union XCERF_REG XCERF; // 27, MCBSP Transmit channel enable partition F
union RCERG_REG RCERG; // 28, MCBSP Receive channel enable partition G
union RCERH_REG RCERH; // 29, MCBSP Receive channel enable partition H
union XCERG_REG XCERG; // 30, MCBSP Transmit channel enable partition G
union XCERH_REG XCERH; // 31, MCBSP Transmit channel enable partition H
Uint16 rsvd1; // 32, reserved
union MFFTX_REG MFFTX; // 33, MCBSP Transmit FIFO register bits
union MFFRX_REG MFFRX; // 34, MCBSP Receive FIFO register bits
union MFFCT_REG MFFCT; // 35, MCBSP FIFO control register bits
union MFFINT_REG MFFINT; // 36, MCBSP Interrupt register bits
union MFFST_REG MFFST; // 37, MCBSP Status register bits
};
//---------------------------------------------------------------------------
// McBSP External References & Function Declarations:
//
extern volatile struct MCBSP_REGS McbspRegs;
#endif // end of DSP28_MCBSP_H definition
//===========================================================================
// No more.
//===========================================================================
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