?? 2410iis.c
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//====================================================================
// File Name : 2410iis.c
// Function : S3C2410 IIS (UDA1341) Record & Play Test Program
// (DMA2, Double Buffer, Record, Play)
// Program : Shin, On Pil (SOP)
// Date : October 01, 2002
// Version : 0.0
// History
// 0.0 : Programming start (March 06, 2002) -> SOP
// 0.1 : Added Slave mode Test Program(July 24, 2002) -> KWT(Tark), SOP
// Optimization (December 09, 2002) -> SOP
//====================================================================
#include "2410addr.h"
#include "2410lib.h"
#include "def.h"
#include "2410iis.h"
void ChangeDMA2(void);
void IIS_PortSetting(void);
void _WrL3Addr(U8 data);
void _WrL3Data(U8 data,int halt);
static void AdjVolume(U8 dir);
static void PlayPause(void);
static void Muting(void);
void __irq DMA2_Done(void);
void __irq DMA2_Rec_Done(void);
void __irq RxInt(void);
#define L3C (1<<4) //GPB4 = L3CLOCK
#define L3D (1<<3) //GPB3 = L3DATA
#define L3M (1<<2) //GPB2 = L3MODE
#define PLAY 0
#define RECORD 1
#define REC_LEN 0x80000 //512K Bytes
//#define REC_LEN 0x100000 //1,048,576 Bytes
#define DataCount 0x10000 //IIS Master/Slave Data Rx/Tx Count
#define DataDisplay 0x100 //IIS Master Data Display Count
//#define DataDisplay 0x10000 //IIS Master Data Display Count
//#define DataCount 0x100 //IIS Master/Slave Data Rx/Tx Count
#define PollMode 0 //1: Polling Mode
#define DMA2Mode 1 //1: DMA2 Mode
unsigned char *Buf,*_temp;
unsigned short *rec_buf;
volatile unsigned int size = 0;
volatile unsigned int fs = 0;
volatile char which_Buf = 1;
volatile char Rec_Done = 0;
volatile char mute = 1;
//------------------------------------------------------------------------------
// SMDK2410 IIS Configuration
// GPB4 = L3CLOCK, GPB3 = L3DATA, GPB2 = L3MODE
// GPE4 = I2SSDO, GPE3 = I2SSDI, GPE2 = CDCLK, GPE1 = I2SSCLK, GPE0 = I2SLRCK
//------------------------------------------------------------------------------
extern U32 downloadFileSize;
extern U32 downloadAddress;
//*********************[ Test_Iis ] *********************************
void Test_Iis(void)
{
unsigned int save_B, save_E, save_PB, save_PE;
Uart_TxEmpty(1);//Uart_TxEmpty(0);
ChangeClockDivider(1,1); //1:2:4
ChangeMPllValue(0x96,0x5,0x1); //FCLK=135.428571MHz (PCLK=33.857142MHz)
Uart_Init(33857142,115200);
Uart_Printf("[ IIS test (Play) using UDA1341 CODEC ]\n");
save_B = rGPBCON;
save_E = rGPECON;
save_PB = rGPBUP;
save_PE = rGPEUP;
IIS_PortSetting();
pISR_UART0 = (unsigned)RxInt; //串口接收數據中斷
pISR_DMA2 = (unsigned)DMA2_Done;
ClearPending(BIT_UART0);
ClearPending(BIT_DMA2);
EnableSubIrq(BIT_SUB_RXD0);//rINTSUBMSK = ~(BIT_SUB_RXD0);
EnableIrq(BIT_DMA2);//rINTMSK = ~(BIT_EINT0 | BIT_UART0 | BIT_DMA2);
//Non-cacheable area = 0x31000000 ~ 0x33feffff
size = downloadFileSize;
Buf = (U8 *)downloadAddress;
printf("\nFile length = %d, Address = 0x%x\n", size-10, Buf);
size = *(U32 *)(Buf+0x28);
fs = *(U32 *)(Buf+0x18);
printf("Sample Size = %d\n",size);
printf("Sampling Frequency = %d Hz\n",fs);
// printf("Press any key to play...\n");
// printf("If you want to mute or no mute push the 'EIN0' key repeatedly\n");
// getch();
Init1341(PLAY);
//DMA2 Initialize
rDISRC2 = (int)(Buf + 0x30); //0x31000030~(Remove header)
rDISRCC2 = (0<<1) + (0<<0); //The source is in the system bus(AHB), Increment
rDIDST2 = ((U32)IISFIFO); //IISFIFO
rDIDSTC2 = (1<<1) + (1<<0); //The destination is in the peripheral bus(APB), Fixed
rDCON2 = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(0<<24)+(1<<23)+(0<<22)+(1<<20)+(size/4);
//1010 0000 1001 xxxx xxxx xxxx xxxx xxxx
//Handshake[31], Sync PCLK[30], CURR_TC Interrupt Request[29], Single Tx[28], Single service[27],
//I2SSDO[26:24], DMA source selected[23],Auto-reload[22], Half-word[21:20], size/2[19:0]
rDMASKTRIG2 = (0<<2) + (1<<1) + (0<<0); //No-stop[2], DMA2 channel On[1], No-sw trigger[0]
//IIS Initialize
if(fs==44100) //11.2896MHz(256fs)
rIISPSR = (2<<5) + 2; //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)
else //fs=22050, 5.6448MHz(256fs)
rIISPSR = (5<<5) + 5; //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)
rIISCON = (1<<5) + (1<<2) + (1<<1); //Tx DMA enable[5], Rx idle[2], Prescaler enable[1]
//Master mode[8],Tx mode[7:6],Low for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
rIISFCON = (1<<15) + (1<<13); //Tx DMA,Tx FIFO --> start piling....
puts("Press 'q' to exit!\n");
puts("Press '+' to increase volume, '-' to decrease volume, 'm' to mute or unmute, 'p' to pause or resume\n");
//IIS Tx Start
rIISCON |= 0x1; //IIS Interface start
while(1)
{
U8 key = getkey();
if(key=='q'||key=='Q')
break;
if(key=='+')
AdjVolume(0);
if(key=='-')
AdjVolume(1);
if(key=='m'||key=='M')
Muting();
if(key=='p'||key=='P')
PlayPause();
if((rDSTAT2 & 0xfffff) < (size/6))
ChangeDMA2();
}
// {
// if((rDSTAT2 & 0xfffff) < (size/6))
// ChangeDMA2();
// }
//IIS Tx Stop
Delay(10); //For end of H/W Tx
rIISCON = 0x0; //IIS Interface stop
rDMASKTRIG2 = (1<<2); //DMA2 stop
rIISFCON = 0x0; //For FIFO flush
size = 0;
rGPBCON = save_B;
rGPECON = save_E;
rGPBUP = save_PB;
rGPEUP = save_PE;
DisableIrq(BIT_DMA2);//rINTMSK = (BIT_DMA2 | BIT_EINT0);
ChangeMPllValue(112, 4, 1); // FCLK=202.8MHz
Uart_Init(0, 115200);
mute = 1;
}
//**************** [ Record_Iis ] ***************************************
void Record_Iis(void)
{
unsigned int save_B, save_E, save_PB, save_PE;
Uart_TxEmpty(0);
ChangeClockDivider(1,1); //1:2:4
ChangeMPllValue(0x96,0x5,0x1); //FCLK=135428571Hz, PCLK=3.385714MHz, 33.857142MHz
Uart_Init(33857142,115200);
Uart_Printf("[ Record test using UDA1341 ]\n");
save_B = rGPBCON;
save_E = rGPECON;
save_PB = rGPBUP;
save_PE = rGPEUP;
IIS_PortSetting();
//Record Buf initialize, Non-cacheable area = 0x31000000 ~ 0x33feffff
rec_buf = (unsigned short *)0x31000000;
pISR_DMA2 = (unsigned)DMA2_Rec_Done;
pISR_EINT0 = (unsigned)Muting;
rINTMSK = ~(BIT_DMA2);
Init1341(RECORD);
//--- DMA2 Initialize
rDISRCC2 = (1<<1) + (1<<0); //APB, Fix
rDISRC2 = ((U32)IISFIFO); //IISFIFO
rDIDSTC2 = (0<<1) + (0<<0); //PHB, Increment
rDIDST2 = (int)rec_buf; //0x31000000 ~
rDCON2 = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(1<<24)+(1<<23)+(1<<22)+(1<<20)+REC_LEN;
//Handshake, sync PCLK, TC int, single tx, single service, I2SSDI, I2S Rx request,
//Off-reload, half-word, 0x50000 half word.
rDMASKTRIG2 = (0<<2) + (1<<1) + 0; //No-stop, DMA2 channel on, No-sw trigger
//IIS Initialize
//Master,Rx,L-ch=low,IIS,16bit ch,CDCLK=256fs,IISCLK=32fs
rIISMOD = (0<<8) + (1<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
rIISPSR = (2<<5) + 2; //Prescaler_A/B=2 <- FCLK 135.4752MHz(1:2:4),11.2896MHz(256fs),44.1KHz
rIISCON = (0<<5) + (1<<4) + (1<<3) + (0<<2) + (1<<1);
//Tx DMA disable,Rx DMA enable,Tx idle,Rx not idle,prescaler enable,stop
rIISFCON = (1<<14) + (1<<12); //Rx DMA,Rx FIFO --> start piling....
Uart_Printf("Press any key to start record!!!\n");
Uart_Getch();
Uart_Printf("Recording...\n");
//Rx start
rIISCON |= 0x1;
while(!Rec_Done);
rINTMSK = BIT_DMA2;
Rec_Done = 0;
//IIS Stop
Delay(10); //For end of H/W Rx
rIISCON = 0x0; //IIS stop
rDMASKTRIG2 = (1<<2); //DMA2 stop
rIISFCON = 0x0; //For FIFO flush
Uart_Printf("End of Record!!!\n");
Uart_Printf("Press any key to play recorded data\n");
Uart_Printf("If you want to mute or no mute push the 'EIN0' key repeatedly\n");
Uart_Getch();
size = REC_LEN * 2;
Uart_Printf("Size = %d\n",size);
Init1341(PLAY);
pISR_DMA2 = (unsigned)DMA2_Done;
rINTMSK = ~(BIT_DMA2 | BIT_EINT0);
//DMA2 Initialize
rDISRCC2 = (0<<1) + (0<<0); //AHB, Increment
rDISRC2 = (int)rec_buf; //0x31000000
rDIDSTC2 = (1<<1) + (1<<0); //APB, Fixed
rDIDST2 = ((U32)IISFIFO); //IISFIFO
rDCON2 = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(0<<24)+(1<<23)+(0<<22)+(1<<20)+(size/2);
//Handshake, sync PCLK, TC int, single tx, single service, I2SSDO, I2S request,
//Auto-reload, half-word, size/2
rDMASKTRIG2 = (0<<2)+(1<<1)+0; //No-stop, DMA2 channel on, No-sw trigger
//IIS Initialize
//Master,Tx,L-ch=low,iis,16bit ch.,CDCLK=256fs,IISCLK=32fs
rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
// rIISPSR = (4<<5) + 4; //Prescaler_A/B=4 for 11.2896MHz
rIISCON = (1<<5)+(0<<4)+(0<<3)+(1<<2)+(1<<1);
//Tx DMA enable,Tx DMA disable,Tx not idle,Rx idle,prescaler enable,stop
rIISFCON = (1<<15) + (1<<13); //Tx DMA,Tx FIFO --> start piling....
Uart_Printf("Press any key to exit!!!\n");
rIISCON |= 0x1; //IIS Tx Start
while(!Uart_GetKey());
//IIS Tx Stop
Delay(10); //For end of H/W Tx
rIISCON = 0x0; //IIS stop
rDMASKTRIG2 = (1<<2); //DMA2 stop
rIISFCON = 0x0; //For FIFO flush
size = 0;
rGPBCON = save_B;
rGPECON = save_E;
rGPBUP = save_PB;
rGPEUP = save_PE;
rINTMSK = (BIT_DMA2 | BIT_EINT0);
ChangeMPllValue(0xa1,0x3,0x1); // FCLK=202.8MHz
Uart_Init(0,115200);
mute = 1;
}
//******************[ Init1341 ]**************************************
void Init1341(char mode)
{
//Port Initialize
//----------------------------------------------------------
// PORT B GROUP
//Ports : GPB4 GPB3 GPB2
//Signal : L3CLOCK L3DATA L3MODE
//Setting: OUTPUT OUTPUT OUTPUT
// [9:8] [7:6} [5:4]
//Binary : 01 , 01 01
//----------------------------------------------------------
rGPBDAT = rGPBDAT & ~(L3M|L3C|L3D) |(L3M|L3C); //Start condition : L3M=H, L3C=H
rGPBUP = rGPBUP & ~(0x7<<2) |(0x7<<2); //The pull up function is disabled GPB[4:2] 1 1100
rGPBCON = rGPBCON & ~(0x3f<<4) |(0x15<<4); //GPB[4:2]=Output(L3CLOCK):Output(L3DATA):Output(L3MODE)
//L3 Interface
_WrL3Addr(0x14 + 2); //STATUS (000101xx+10)
_WrL3Data(0x60,0); //0,1,10, 000,0 : Status 0,Reset,256fs,IIS-bus,no DC-filtering
_WrL3Addr(0x14 + 2); //STATUS (000101xx+10)
_WrL3Data(0x20,0); //0,0,10, 000,0 : Status 0,No reset,256fs,IIS-bus,no DC-filtering
_WrL3Addr(0x14 + 2); //STATUS (000101xx+10)
_WrL3Data(0x81,0); //1,0,0,0, 0,0,01
//Status 1,Gain of DAC 0 dB,Gain of ADC 0dB,ADC non-inverting,DAC non-inverting
//,Single speed playback,ADC-Off DAC-On
//Record
if(mode)
{
_WrL3Addr(0x14 + 2); //STATUS (000101xx+10)
// _WrL3Data(0xa2,0); //1,0,1,0, 0,0,10
//Status 1,Gain of DAC 0 dB,Gain of ADC 6dB,ADC non-inverting,DAC non-inverting
//,Single speed playback,ADC-On DAC-Off
_WrL3Data(0xe3,0); //1,1,1,0, 0,0,11
//Status 1,Gain of DAC 6 dB,Gain of ADC 6dB,ADC non-inverting,DAC non-inverting
//,Single speed playback,ADC-On DAC-On
// _WrL3Addr(0x14 + 0); //DATA0 (000101xx+00)
// _WrL3Data(0x3f,0); //00,11 1111 : Volume control (6 bits)
// _WrL3Data(0x00,0); //00,00 0000 : Volume control (6 bits) 0dB
_WrL3Addr(0x14 + 0); //DATA0 (000101xx+00)
_WrL3Data(0x7b,0); //01,11 10,11 : Data0, Bass Boost 18~24dB, Treble 6dB
// _WrL3Addr(0x14 + 0); //DATA0 (000101xx+00)
_WrL3Data(0xc4,0); //1100 0,100 : Extended addr(3bits), 100
_WrL3Data(0x91,0); //100,1 00,01 : DATA0, Enable AGC, 00, input amplifier gain channel 2 (2bits)
// _WrL3Addr(0x14 + 0); //DATA0 (000101xx+00)
_WrL3Data(0xc2,0); //1100 0,010 : Extended addr(3bits), 010
// _WrL3Data(0x4d,0); //010,0 11,01 : DATA0, MIC Amplifier Gain 9dB, input channel 1 select(input channel 2 off)
_WrL3Data(0x59,0); //010,1 10,01 : DATA0, MIC Amplifier Gain 27dB, input channel 1 select(input channel 2 off)
// _WrL3Data(0x41,0); //010,0 00,01 : DATA0, MIC Amplifier Gain -3dB, input channel 1 select(input channel 2 off)
}
}
#define MAX_VOLUME 60
static void AdjVolume(U8 dir) // dir = 0 -> + , dir = 1 -> -
{
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