# 8051-c.ini
#
# ARCH = < 8051 | 80C517 | 80C751 >
#	8051 means standard architecture
#	80C517 means has 32-Bit ALU
#	80C751 is a chip whose maximum program size < 2048. Therefore some instructions
#	are not implimented.
# MAKE = <string>
#	Name of manufacturer of this chip.
# INTRAM = <hex_value>
#	Defines the upper limit of on-chip internal RAM which may be accessed indirectly.
#	Possible values are 40 (64bytes) ,80 (128bytes) ,C0 (192bytes) or 100 (256bytes).
# XRAM = <start address-end address>
#	How much on-chip, external data memory is available?
#	If XRAM is not defined, then chip's entire data memory will be located
#	in external memory.
# OFFRAM = <start address-end address>
#	Range of off-chip external data that can be added.
#	If OFFRAM is not defined, then external data is not available
#	for this chip. Therefore this chip's entire data memory cannot be expanded
#	from the value of XRAM.
# ROM = <start address-end address>
#	How much program memory is available on-board the chip?
#	If ROM is not defined, then chip's entire program memory will be located
#	in external memory.
# OFFROM = <start address-end address>
#	The range of addressable program memory.
#	Range of addressable data memory.
#	If OFFROM is not defined, then external prog memory is not available
#	for this chip. Therefore this chip's prog memory cannot be expanded
#	from the ranges defined by ROM.
# BANKS = <first supported bank,total number of banks supported>
#	For chips that have supported banking ability, this attribute defines the
#	first bank which is supported by the compiler. A bank may not be selectable
#	if it is already part of the common ROM area.
# BANKADR = <start address-end address>
#	The range where the banked memory can be found. This is defined only 
#	for those chips who support banked memory.
# BANKTYPE = < C | A | Z | G | T | F | U | V | N | E >
#	This criteria describes the method used when performing a bank switch.
#	Note that N is a special case that is reserved.
# INSTR = <set>
#	Describes which instruction set the chip uses. Any deviations from
#	the standard insruction set will be noted here. The standard
#	instruction set is called MCS-51.

[8031AH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8032AH]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8044]
MAKE = INTEL
INTRAM = C0
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8051]
MAKE = GENERIC
INTRAM = 100
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
BANKS = 0,8
BANKADR = 8000-FFFF
BANKTYPE = N
INSTR = MCS-51
ARCH = 8051

[8051AH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8051AHP]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-0FFF
ROM = 0-0FFF
OFFROM = 0-0FFF
INSTR = MCS-51
ARCH = 8051
# protected version of 8051AH: prog verify disabled, limited ext access

[8052AH]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C151SA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has page mode

[80C151SB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has page mode

[80C152]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C152JA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C152JB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C152JC]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C152JD]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C31BH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C32]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51BH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51BHP]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-0FFF
ROM = 0-0FFF
OFFROM = 0-0FFF
INSTR = MCS-51
ARCH = 8051
# protected version of 80C51BH: prog verify disabled, limited extern access

[80C51FA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51GB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51RA]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C517]
MAKE = GENERIC
INTRAM = 100
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517

[80C52]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C537]
MAKE = GENERIC
INTRAM = 100
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517

[80C54]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C58]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C751]
MAKE = GENERIC
INTRAM = 100
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

[8344]
MAKE = INTEL
INTRAM = C0
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C151SA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C151SB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152JA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152JB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152JC]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152JD]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51FA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51FB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51FC]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51KB]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51RA]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51RB]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51RC]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8744]
MAKE = INTEL
INTRAM = C0
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8751BH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8751H]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8751H8]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 8Mhz version of 8751H

[8752BH]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C151SA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C151SB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51FA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51FB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51FC]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51GB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51RA]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51RB]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51RC]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C52]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C54]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C58]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[ADUC812]
MAKE = ANALOG_DEVICES
INTRAM = 100
XRAM = 0-9F
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has both data SRAM and data flash/EE on chip, this chip has 24-Bit addressing for data (we will support up to 16-Bit)
# data Flash/EE addressed between 0-9F can be paged. Under SFR control. 

[ADUC812S]
MAKE = ANALOG_DEVICES
INTRAM = 100
XRAM = 0-9F
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has both data RAM and data flash/EE on chip
# data Flash/EE addressed between 0-9F can be paged. Under SFR control. 

[ADUC814]
MAKE = ANALOG_DEVICES
INTRAM = 100
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has 640 bytes of EEPROM data memory

[ADUC816]
MAKE = ANALOG_DEVICES
INTRAM = 80
XRAM = 0-9F
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has both data RAM and data flash/EE on chip, this chip has 24-Bit addressing for data (we will only support 16-Bits)
# data Flash/EE addressed between 0-9F can be paged. Under SFR control. 

[ADUC824]
MAKE = ANALOG_DEVICES
INTRAM = 100
XRAM = 0-9F
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has both data RAM and data flash/EE on chip, this chip has 24-Bit addressing for data (we will only support 16-Bits)
# data Flash/EE addressed between 0-9F can be paged. Under SFR control. 

[ADUC831]
MAKE = ANALOG_DEVICES
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-F7FF
INSTR = MCS-51
ARCH = 8051
# has 4k of EEPROM data memory
# can access up to 16MB of external data memory
# has XRAM at 0-7FF, but is disabled by default, enabled via CFG831 sfr.

[ADUC832]
MAKE = ANALOG_DEVICES
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-F7FF
INSTR = MCS-51
ARCH = 8051
# has 4k of EEPROM data memory
# can access up to 16MB of external data memory
# has XRAM at 0-7FF, but is disabled by default, enabled via CFG832 sfr.

[ADUC834]
MAKE = ANALOG_DEVICES
INTRAM = 100
ROM = 0-F7FF
OFFRAM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4k of EEPROM data memory
# can access up to 16MB of external data memory
# has XRAM at 0-7FF, but is disabled by default, enabled via CFG834 sfr.

[ADUC836]
MAKE = ANALOG_DEVICES
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-F7FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# WARNING - this chip does not support rollover execution between
#           on-chip and off-chip program memory! IE use one or the
#           other - not both.
# can access up to 16MB of external data memory

[ADUC841]
MAKE = ANALOG_DEVICES
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-F7FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# WARNING - this chip does not support rollover execution between
#           on-chip and off-chip program memory! IE use one or the
#           other - not both.
# can access up to 16MB of external data memory

[ADUC842]
MAKE = ANALOG_DEVICES
INTRAM = 100