?? f2407_c.h
字號(hào):
/***********************************************************************************
* FILE:TYPEDEFS.H *
* TMS320LF2407A TEST BED CODE *
* ZHEJIANG TIANHUANG TECHNOLOGY INDUSTRIAL CO.,Ltd *
* 07/28/2006 Vesion 1.0 *
* Jzming *
***********************************************************************************/
#ifndef _F2407_c_H
#define _F2407_c_H
/* Core registers */
#define IMR ((PORT)0x0004)
#define GREG ((PORT)0x0005) /* Global memory allocation reg */
#define IFR ((PORT)0x0006) /* Interrupt flag reg */
#define WSGR ((PORT)0xFFFF)
/* System configuration and interrupt registers */
#define PIRQR0 ((PORT)0x7010) /* Peripheral interrupt request reg 0 */
#define PIRQR1 ((PORT)0x7011) /* Peripheral interrupt request reg 1 */
#define PIRQR2 ((PORT)0x7012) /* Peripheral interrupt request reg 2 */
#define PIACKR0 ((PORT)0x7014) /* Peripheral interrupt acknowledge reg 0 */
#define PIACKR1 ((PORT)0x7015) /* Peripheral interrupt acknowledge reg 1 */
#define PIACKR2 ((PORT)0x7016) /* Peripheral interrupt acknowledge reg 2 */
#define SCSR1 ((PORT)0x7018) /* System control & status reg 1 */
#define SCSR2 ((PORT)0x7019) /* System control & status reg 2 */
#define DINR ((PORT)0x701C) /* Device identification reg */
#define PIVR ((PORT)0x701E) /* Peripheral interrupt vector reg */
/* Watchdog timer *(WD) registers */
#define WDCNTR ((PORT)0x7023) /* WD counter reg */
#define WDKEY ((PORT)0x7025) /* WD reset key reg */
#define WDCR ((PORT)0x7029) /* WD timer control reg */
/* Serial Peripheral Interface *(SPI) registers */
#define SPICCR ((PORT)0x7040) /* SPI configuration control reg */
#define SPICTL ((PORT)0x7041) /* SPI operation control reg */
#define SPISTS ((PORT)0x7042) /* SPI status reg */
#define SPIBRR ((PORT)0x7044) /* SPI baud rate reg */
#define SPIRXEMU ((PORT)0x7046) /* SPI emulation buffer reg */
#define SPIRXBUF ((PORT)0x7047) /* SPI serial receive buffer reg */
#define SPITXBUF ((PORT)0x7048) /* SPI serial transmit buffer reg */
#define SPIDAT ((PORT)0x7049) /* SPI serial data reg */
#define SPIPRI ((PORT)0x704F) /* SPI priority control reg */
/* SCI registers */
#define SCICCR ((PORT)0x7050) /* SCI communication control reg */
#define SCICTL1 ((PORT)0x7051) /* SCI control reg 1 */
#define SCIHBAUD ((PORT)0x7052) /* SCI baud-select reg, high bits */
#define SCILBAUD ((PORT)0x7053) /* SCI baud-select reg, low bits */
#define SCICTL2 ((PORT)0x7054) /* SCI control reg 2 */
#define SCIRXST ((PORT)0x7055) /* SCI receiver status reg */
#define SCIRXEMU ((PORT)0x7056) /* SCI emulation data buffer reg */
#define SCIRXBUF ((PORT)0x7057) /* SCI receiver data buffer reg */
#define SCITXBUF ((PORT)0x7059) /* SCI transmit data buffer reg */
#define SCIPRI ((PORT)0x705F) /* SCI priority control reg */
/* External interrupt configuration registers */
#define XINT1CR ((PORT)0x7070) /* Ext interrupt 1 config reg */
#define XINT2CR ((PORT)0x7071) /* Ext interrupt 2 config reg */
/* Digital I/O registers */
#define MCRA ((PORT)0x7090) /* I/O mux control reg A */
#define MCRB ((PORT)0x7092) /* I/O mux control reg B */
#define MCRC ((PORT)0x7094) /* I/O mux control reg C */
#define PADATDIR ((PORT)0x7098) /* I/O port A data & dir reg */
#define PBDATDIR ((PORT)0x709A) /* I/O port B data & dir reg */
#define PCDATDIR ((PORT)0x709C) /* I/O port C data & dir reg */
#define PDDATDIR ((PORT)0x709E) /* I/O port D data & dir reg */
#define PEDATDIR ((PORT)0x7095) /* I/O port E data & dir reg */
#define PFDATDIR ((PORT)0x7096) /* I/O port F data & dir reg */
/* Analog-to-Digital Converter *(ADC) registers */
#define ADCTRL1 ((PORT)0x70A0) /* ADC control reg 1 */
#define ADCTRL2 ((PORT)0x70A1) /* ADC control reg 2 */
#define MAX_CONV ((PORT)0x70A2) /* Maximum conversion channels reg */
#define CHSELSEQ1 ((PORT)0x70A3) /* Channel select sequencing control reg 1 */
#define CHSELSEQ2 ((PORT)0x70A4) /* Channel select sequencing control reg 2 */
#define CHSELSEQ3 ((PORT)0x70A5) /* Channel select sequencing control reg 3 */
#define CHSELSEQ4 ((PORT)0x70A6) /* Channel select sequencing control reg 4 */
#define AUTO_SEQ_SR ((PORT)0x70A7) /* Autosequence status reg */
#define RESULT0 ((PORT)0x70A8) /* Conversion result buffer reg 0 */
#define RESULT1 ((PORT)0x70A9) /* Conversion result buffer reg 1 */
#define RESULT2 ((PORT)0x70AA) /* Conversion result buffer reg 2 */
#define RESULT3 ((PORT)0x70AB) /* Conversion result buffer reg 3 */
#define RESULT4 ((PORT)0x70AC) /* Conversion result buffer reg 4 */
#define RESULT5 ((PORT)0x70AD) /* Conversion result buffer reg 5 */
#define RESULT6 ((PORT)0x70AE) /* Conversion result buffer reg 6 */
#define RESULT7 ((PORT)0x70AF) /* Conversion result buffer reg 7 */
#define RESULT8 ((PORT)0x70B0) /* Conversion result buffer reg 8 */
#define RESULT9 ((PORT)0x70B1) /* Conversion result buffer reg 9 */
#define RESULT10 ((PORT)0x70B2) /* Conversion result buffer reg 10 */
#define RESULT11 ((PORT)0x70B3) /* Conversion result buffer reg 11 */
#define RESULT12 ((PORT)0x70B4) /* Conversion result buffer reg 12 */
#define RESULT13 ((PORT)0x70B5) /* Conversion result buffer reg 13 */
#define RESULT14 ((PORT)0x70B6) /* Conversion result buffer reg 14 */
#define RESULT15 ((PORT)0x70B7) /* Conversion result buffer reg 15 */
#define CALIBRATION ((PORT)0x70B8) /* Calibration result reg */
/* Controller Area Network *(CAN) registers */
#define MDER ((PORT)0x7100) /* CAN mailbox direction/enable reg */
#define TCR ((PORT)0x7101) /* CAN transmission control reg */
#define RCR ((PORT)0x7102) /* CAN receive control reg */
#define MCR ((PORT)0x7103) /* CAN master control reg */
#define BCR2 ((PORT)0x7104) /* CAN bit config reg 2 */
#define BCR1 ((PORT)0x7105) /* CAN bit config reg 1 */
#define ESR ((PORT)0x7106) /* CAN error status reg */
#define GSR ((PORT)0x7107) /* CAN global status reg */
#define CEC ((PORT)0x7108) /* CAN trans and rcv err counters */
#define CAN_IFR ((PORT)0x7109) /* CAN interrupt flag reg */
#define CAN_IMR ((PORT)0x710a) /* CAN interrupt mask reg */
#define LAM0_H ((PORT)0x710b) /* CAN local acceptance mask MBX0/1 */
#define LAM0_L ((PORT)0x710c) /* CAN local acceptance mask MBX0/1 */
#define LAM1_H ((PORT)0x710d) /* CAN local acceptance mask MBX2/3 */
#define LAM1_L ((PORT)0x710e) /* CAN local acceptance mask MBX2/3 */
#define MSGID0L ((PORT)0x7200) /* CAN message ID for mailbox 0 *(lower 16 bits) */
#define MSGID0H ((PORT)0x7201) /* CAN message ID for mailbox 0 *(upper 16 bits) */
#define MSGCTRL0 ((PORT)0x7202) /* CAN RTR and DLC for mailbox 0 */
#define MBX0A ((PORT)0x7204) /* CAN 2 of 8 bytes of mailbox 0 */
#define MBX0B ((PORT)0x7205) /* CAN 2 of 8 bytes of mailbox 0 */
#define MBX0C ((PORT)0x7206) /* CAN 2 of 8 bytes of mailbox 0 */
#define MBX0D ((PORT)0x7207) /* CAN 2 of 8 bytes of mailbox 0 */
#define MSGID1L ((PORT)0x7208) /* CAN message ID for mailbox 1 *(lower 16 bits) */
#define MSGID1H ((PORT)0x7209) /* CAN message ID for mailbox 1 *(upper 16 bits) */
#define MSGCTRL1 ((PORT)0x720A) /* CAN RTR and DLC for mailbox 1 */
#define MBX1A ((PORT)0x720C) /* CAN 2 of 8 bytes of mailbox 1 */
#define MBX1B ((PORT)0x720D) /* CAN 2 of 8 bytes of mailbox 1 */
#define MBX1C ((PORT)0x720E) /* CAN 2 of 8 bytes of mailbox 1 */
#define MBX1D ((PORT)0x720F) /* CAN 2 of 8 bytes of mailbox 1 */
#define MSGID2L ((PORT)0x7210) /* CAN message ID for mailbox 2 *(lower 16 bits) */
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