?? m649def.inc
字號(hào):
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2007-12-13 07:27 ******* Source: ATmega649.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m649def.inc"
;* Title : Register/Bit Definitions for the ATmega649
;* Date : 2007-12-13
;* Version : 2.24
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega649
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _M649DEF_INC_
#define _M649DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATmega649
#pragma AVRPART ADMIN PART_NAME ATmega649
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x96
.equ SIGNATURE_002 = 0x03
#pragma AVRPART CORE CORE_VERSION V2E
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ LCDDR19 = 0xff ; MEMORY MAPPED
.equ LCDDR18 = 0xfe ; MEMORY MAPPED
.equ LCDDR17 = 0xfd ; MEMORY MAPPED
.equ LCDDR16 = 0xfc ; MEMORY MAPPED
.equ LCDDR15 = 0xfb ; MEMORY MAPPED
.equ LCDDR14 = 0xfa ; MEMORY MAPPED
.equ LCDDR13 = 0xf9 ; MEMORY MAPPED
.equ LCDDR12 = 0xf8 ; MEMORY MAPPED
.equ LCDDR11 = 0xf7 ; MEMORY MAPPED
.equ LCDDR10 = 0xf6 ; MEMORY MAPPED
.equ LCDDR9 = 0xf5 ; MEMORY MAPPED
.equ LCDDR8 = 0xf4 ; MEMORY MAPPED
.equ LCDDR7 = 0xf3 ; MEMORY MAPPED
.equ LCDDR6 = 0xf2 ; MEMORY MAPPED
.equ LCDDR5 = 0xf1 ; MEMORY MAPPED
.equ LCDDR4 = 0xf0 ; MEMORY MAPPED
.equ LCDDR3 = 0xef ; MEMORY MAPPED
.equ LCDDR2 = 0xee ; MEMORY MAPPED
.equ LCDDR1 = 0xed ; MEMORY MAPPED
.equ LCDDR0 = 0xec ; MEMORY MAPPED
.equ LCDCCR = 0xe7 ; MEMORY MAPPED
.equ LCDFRR = 0xe6 ; MEMORY MAPPED
.equ LCDCRB = 0xe5 ; MEMORY MAPPED
.equ LCDCRA = 0xe4 ; MEMORY MAPPED
.equ UDR0 = 0xc6 ; MEMORY MAPPED
.equ UBRR0L = 0xc4 ; MEMORY MAPPED
.equ UBRR0H = 0xc5 ; MEMORY MAPPED
.equ UCSR0C = 0xc2 ; MEMORY MAPPED
.equ UCSR0B = 0xc1 ; MEMORY MAPPED
.equ UCSR0A = 0xc0 ; MEMORY MAPPED
.equ USIDR = 0xba ; MEMORY MAPPED
.equ USISR = 0xb9 ; MEMORY MAPPED
.equ USICR = 0xb8 ; MEMORY MAPPED
.equ ASSR = 0xb6 ; MEMORY MAPPED
.equ OCR2A = 0xb3 ; MEMORY MAPPED
.equ TCNT2 = 0xb2 ; MEMORY MAPPED
.equ TCCR2A = 0xb0 ; MEMORY MAPPED
.equ OCR1BL = 0x8a ; MEMORY MAPPED
.equ OCR1BH = 0x8b ; MEMORY MAPPED
.equ OCR1AL = 0x88 ; MEMORY MAPPED
.equ OCR1AH = 0x89 ; MEMORY MAPPED
.equ ICR1L = 0x86 ; MEMORY MAPPED
.equ ICR1H = 0x87 ; MEMORY MAPPED
.equ TCNT1L = 0x84 ; MEMORY MAPPED
.equ TCNT1H = 0x85 ; MEMORY MAPPED
.equ TCCR1C = 0x82 ; MEMORY MAPPED
.equ TCCR1B = 0x81 ; MEMORY MAPPED
.equ TCCR1A = 0x80 ; MEMORY MAPPED
.equ DIDR1 = 0x7f ; MEMORY MAPPED
.equ DIDR0 = 0x7e ; MEMORY MAPPED
.equ ADMUX = 0x7c ; MEMORY MAPPED
.equ ADCSRB = 0x7b ; MEMORY MAPPED
.equ ADCSRA = 0x7a ; MEMORY MAPPED
.equ ADCH = 0x79 ; MEMORY MAPPED
.equ ADCL = 0x78 ; MEMORY MAPPED
.equ TIMSK2 = 0x70 ; MEMORY MAPPED
.equ TIMSK1 = 0x6f ; MEMORY MAPPED
.equ TIMSK0 = 0x6e ; MEMORY MAPPED
.equ PCMSK0 = 0x6b ; MEMORY MAPPED
.equ PCMSK1 = 0x6c ; MEMORY MAPPED
.equ EICRA = 0x69 ; MEMORY MAPPED
.equ OSCCAL = 0x66 ; MEMORY MAPPED
.equ PRR = 0x64 ; MEMORY MAPPED
.equ CLKPR = 0x61 ; MEMORY MAPPED
.equ WDTCR = 0x60 ; MEMORY MAPPED
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ SPMCSR = 0x37
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ SMCR = 0x33
.equ OCDR = 0x31
.equ ACSR = 0x30
.equ SPDR = 0x2e
.equ SPSR = 0x2d
.equ SPCR = 0x2c
.equ GPIOR2 = 0x2b
.equ GPIOR1 = 0x2a
.equ OCR0A = 0x27
.equ TCNT0 = 0x26
.equ TCCR0A = 0x24
.equ GTCCR = 0x23
.equ EEARL = 0x21
.equ EEARH = 0x22
.equ EEDR = 0x20
.equ EECR = 0x1f
.equ GPIOR0 = 0x1e
.equ EIMSK = 0x1d
.equ EIFR = 0x1c
.equ TIFR2 = 0x17
.equ TIFR1 = 0x16
.equ TIFR0 = 0x15
.equ PORTG = 0x14
.equ DDRG = 0x13
.equ PING = 0x12
.equ PORTF = 0x11
.equ DDRF = 0x10
.equ PINF = 0x0f
.equ PORTE = 0x0e
.equ DDRE = 0x0d
.equ PINE = 0x0c
.equ PORTD = 0x0b
.equ DDRD = 0x0a
.equ PIND = 0x09
.equ PORTC = 0x08
.equ DDRC = 0x07
.equ PINC = 0x06
.equ PORTB = 0x05
.equ DDRB = 0x04
.equ PINB = 0x03
.equ PORTA = 0x02
.equ DDRA = 0x01
.equ PINA = 0x00
; ***** BIT DEFINITIONS **************************************************
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
.equ ADLAR = 5 ; Left Adjust Result
.equ REFS0 = 6 ; Reference Selection Bit 0
.equ REFS1 = 7 ; Reference Selection Bit 1
; ADCSRA - The ADC Control and Status register
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADATE = 5 ; ADC Auto Trigger Enable
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
; ADCH - ADC Data Register High Byte
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
; ADCL - ADC Data Register Low Byte
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
; ADCSRB - ADC Control and Status Register B
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
; DIDR0 - Digital Input Disable Register 0
.equ ADC0D = 0 ; ADC0 Digital input Disable
.equ ADC1D = 1 ; ADC1 Digital input Disable
.equ ADC2D = 2 ; ADC2 Digital input Disable
.equ ADC3D = 3 ; ADC3 Digital input Disable
.equ ADC4D = 4 ; ADC4 Digital input Disable
.equ ADC5D = 5 ; ADC5 Digital input Disable
.equ ADC6D = 6 ; ADC6 Digital input Disable
.equ ADC7D = 7 ; ADC7 Digital input Disable
; ***** ANALOG_COMPARATOR ************
; ADCSRB - ADC Control and Status Register B
.equ ACME = 6 ; Analog Comparator Multiplexer Enable
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Compare Output
.equ ACBG = 6 ; Analog Comparator Bandgap Select
.equ ACD = 7 ; Analog Comparator Disable
; DIDR1 - Digital Input Disable Register 1
.equ AIN0D = 0 ; AIN0 Digital Input Disable
.equ AIN1D = 1 ; AIN1 Digital Input Disable
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
; ***** USI **************************
; USIDR - USI Data Register
.equ USIDR0 = 0 ; USI Data Register bit 0
.equ USIDR1 = 1 ; USI Data Register bit 1
.equ USIDR2 = 2 ; USI Data Register bit 2
.equ USIDR3 = 3 ; USI Data Register bit 3
.equ USIDR4 = 4 ; USI Data Register bit 4
.equ USIDR5 = 5 ; USI Data Register bit 5
.equ USIDR6 = 6 ; USI Data Register bit 6
.equ USIDR7 = 7 ; USI Data Register bit 7
; USISR - USI Status Register
.equ USICNT0 = 0 ; USI Counter Value Bit 0
.equ USICNT1 = 1 ; USI Counter Value Bit 1
.equ USICNT2 = 2 ; USI Counter Value Bit 2
.equ USICNT3 = 3 ; USI Counter Value Bit 3
.equ USIDC = 4 ; Data Output Collision
.equ USIPF = 5 ; Stop Condition Flag
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
.equ USISIF = 7 ; Start Condition Interrupt Flag
; USICR - USI Control Register
.equ USITC = 0 ; Toggle Clock Port Pin
.equ USICLK = 1 ; Clock Strobe
.equ USICS0 = 2 ; USI Clock Source Select Bit 0
.equ USICS1 = 3 ; USI Clock Source Select Bit 1
.equ USIWM0 = 4 ; USI Wire Mode Bit 0
.equ USIWM1 = 5 ; USI Wire Mode Bit 1
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
.equ USISIE = 7 ; Start Condition Interrupt Enable
; ***** USART0 ***********************
; UDR0 - USART I/O Data Register
.equ UDR = UDR0 ; For compatibility
.equ UDR00 = 0 ; USART I/O Data Register bit 0
.equ UDR01 = 1 ; USART I/O Data Register bit 1
.equ UDR02 = 2 ; USART I/O Data Register bit 2
.equ UDR03 = 3 ; USART I/O Data Register bit 3
.equ UDR04 = 4 ; USART I/O Data Register bit 4
.equ UDR05 = 5 ; USART I/O Data Register bit 5
.equ UDR06 = 6 ; USART I/O Data Register bit 6
.equ UDR07 = 7 ; USART I/O Data Register bit 7
; UCSR0A - USART Control and Status Register A
.equ UCSRA = UCSR0A ; For compatibility
.equ USR = UCSR0A ; For compatibility
.equ MPCM0 = 0 ; Multi-processor Communication Mode
.equ MPCM = MPCM0 ; For compatibility
.equ U2X0 = 1 ; Double the USART Transmission Speed
.equ U2X = U2X0 ; For compatibility
.equ UPE0 = 2 ; USART Parity Error
.equ UPE = UPE0 ; For compatibility
.equ DOR0 = 3 ; Data OverRun
.equ DOR = DOR0 ; For compatibility
.equ FE0 = 4 ; Framing Error
.equ FE = FE0 ; For compatibility
.equ UDRE0 = 5 ; USART Data Register Empty
.equ UDRE = UDRE0 ; For compatibility
.equ TXC0 = 6 ; USART Transmit Complete
.equ TXC = TXC0 ; For compatibility
.equ RXC0 = 7 ; USART Receive Complete
.equ RXC = RXC0 ; For compatibility
; UCSR0B - USART Control and Status Register B
.equ UCSRB = UCSR0B ; For compatibility
.equ UCR = UCSR0B ; For compatibility
.equ TXB80 = 0 ; Transmit Data Bit 8
.equ TXB8 = TXB80 ; For compatibility
.equ RXB80 = 1 ; Receive Data Bit 8
.equ RXB8 = RXB80 ; For compatibility
.equ UCSZ02 = 2 ; Character Size
.equ UCSZ2 = UCSZ02 ; For compatibility
.equ TXEN0 = 3 ; Transmitter Enable
.equ TXEN = TXEN0 ; For compatibility
.equ RXEN0 = 4 ; Receiver Enable
.equ RXEN = RXEN0 ; For compatibility
.equ UDRIE0 = 5 ; USART Data Register Empty Interrupt Enable
.equ UDRIE = UDRIE0 ; For compatibility
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable
.equ TXCIE = TXCIE0 ; For compatibility
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable
.equ RXCIE = RXCIE0 ; For compatibility
; UCSR0C - USART Control and Status Register C
.equ UCSRC = UCSR0C ; For compatibility
.equ UCPOL0 = 0 ; Clock Polarity
.equ UCPOL = UCPOL0 ; For compatibility
.equ UCSZ00 = 1 ; Character Size
.equ UCSZ0 = UCSZ00 ; For compatibility
.equ UCSZ01 = 2 ; Character Size
.equ UCSZ1 = UCSZ01 ; For compatibility
.equ USBS0 = 3 ; Stop Bit Select
.equ USBS = USBS0 ; For compatibility
.equ UPM00 = 4 ; Parity Mode Bit 0
.equ UPM0 = UPM00 ; For compatibility
.equ UPM01 = 5 ; Parity Mode Bit 1
.equ UPM1 = UPM01 ; For compatibility
.equ UMSEL0 = 6 ; USART Mode Select
.equ UMSEL = UMSEL0 ; For compatibility
; UBRR0H - USART Baud Rate Register High Byte
.equ UBRRH = UBRR0H ; For compatibility
.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
; UBRR0L - USART Baud Rate Register Low Byte
.equ UBRRL = UBRR0L ; For compatibility
.equ UBRR = UBRR0L ; For compatibility
.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
; MCUCR - MCU Control Register
.equ IVCE = 0 ; Interrupt Vector Change Enable
.equ IVSEL = 1 ; Interrupt Vector Select
.equ PUD = 4 ; Pull-up disable
; MCUSR - MCU Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
.equ JTRF = 4 ; JTAG Reset Flag
?? 快捷鍵說(shuō)明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號(hào)
Ctrl + =
減小字號(hào)
Ctrl + -