?? m649def.inc
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; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
; ***** PORTE ************************
; PORTE - Data Register, Port E
.equ PORTE0 = 0 ;
.equ PE0 = 0 ; For compatibility
.equ PORTE1 = 1 ;
.equ PE1 = 1 ; For compatibility
.equ PORTE2 = 2 ;
.equ PE2 = 2 ; For compatibility
.equ PORTE3 = 3 ;
.equ PE3 = 3 ; For compatibility
.equ PORTE4 = 4 ;
.equ PE4 = 4 ; For compatibility
.equ PORTE5 = 5 ;
.equ PE5 = 5 ; For compatibility
.equ PORTE6 = 6 ;
.equ PE6 = 6 ; For compatibility
.equ PORTE7 = 7 ;
.equ PE7 = 7 ; For compatibility
; DDRE - Data Direction Register, Port E
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
.equ DDE3 = 3 ;
.equ DDE4 = 4 ;
.equ DDE5 = 5 ;
.equ DDE6 = 6 ;
.equ DDE7 = 7 ;
; PINE - Input Pins, Port E
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
.equ PINE3 = 3 ;
.equ PINE4 = 4 ;
.equ PINE5 = 5 ;
.equ PINE6 = 6 ;
.equ PINE7 = 7 ;
; ***** PORTF ************************
; PORTF - Data Register, Port F
.equ PORTF0 = 0 ;
.equ PF0 = 0 ; For compatibility
.equ PORTF1 = 1 ;
.equ PF1 = 1 ; For compatibility
.equ PORTF2 = 2 ;
.equ PF2 = 2 ; For compatibility
.equ PORTF3 = 3 ;
.equ PF3 = 3 ; For compatibility
.equ PORTF4 = 4 ;
.equ PF4 = 4 ; For compatibility
.equ PORTF5 = 5 ;
.equ PF5 = 5 ; For compatibility
.equ PORTF6 = 6 ;
.equ PF6 = 6 ; For compatibility
.equ PORTF7 = 7 ;
.equ PF7 = 7 ; For compatibility
; DDRF - Data Direction Register, Port F
.equ DDF0 = 0 ;
.equ DDF1 = 1 ;
.equ DDF2 = 2 ;
.equ DDF3 = 3 ;
.equ DDF4 = 4 ;
.equ DDF5 = 5 ;
.equ DDF6 = 6 ;
.equ DDF7 = 7 ;
; PINF - Input Pins, Port F
.equ PINF0 = 0 ;
.equ PINF1 = 1 ;
.equ PINF2 = 2 ;
.equ PINF3 = 3 ;
.equ PINF4 = 4 ;
.equ PINF5 = 5 ;
.equ PINF6 = 6 ;
.equ PINF7 = 7 ;
; ***** PORTG ************************
; PORTG - Port G Data Register
.equ PORTG0 = 0 ;
.equ PG0 = 0 ; For compatibility
.equ PORTG1 = 1 ;
.equ PG1 = 1 ; For compatibility
.equ PORTG2 = 2 ;
.equ PG2 = 2 ; For compatibility
.equ PORTG3 = 3 ;
.equ PG3 = 3 ; For compatibility
.equ PORTG4 = 4 ;
.equ PG4 = 4 ; For compatibility
; DDRG - Port G Data Direction Register
.equ DDG0 = 0 ;
.equ DDG1 = 1 ;
.equ DDG2 = 2 ;
.equ DDG3 = 3 ;
.equ DDG4 = 4 ;
; PING - Port G Input Pins
.equ PING0 = 0 ;
.equ PING1 = 1 ;
.equ PING2 = 2 ;
.equ PING3 = 3 ;
.equ PING4 = 4 ;
.equ PING5 = 5 ;
; ***** TIMER_COUNTER_0 **************
; TCCR0A - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select 0
.equ CS01 = 1 ; Clock Select 1
.equ CS02 = 2 ; Clock Select 2
.equ WGM01 = 3 ; Waveform Generation Mode 1
.equ COM0A0 = 4 ; Compare match Output Mode 0
.equ COM0A1 = 5 ; Compare Match Output Mode 1
.equ WGM00 = 6 ; Waveform Generation Mode 0
.equ FOC0A = 7 ; Force Output Compare
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCR0A0 = 0 ;
.equ OCR0A1 = 1 ;
.equ OCR0A2 = 2 ;
.equ OCR0A3 = 3 ;
.equ OCR0A4 = 4 ;
.equ OCR0A5 = 5 ;
.equ OCR0A6 = 6 ;
.equ OCR0A7 = 7 ;
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable
; TIFR0 - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0
; GTCCR - General Timer/Control Register
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
.equ PSR10 = PSR310 ; For compatibility
.equ PSR0 = PSR310 ; For compatibility
.equ PSR1 = PSR310 ; For compatibility
.equ PSR3 = PSR310 ; For compatibility
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_1 **************
; TIMSK1 - Timer/Counter1 Interrupt Mask Register
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
; TIFR1 - Timer/Counter1 Interrupt Flag register
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
.equ OCF1A = 1 ; Output Compare Flag 1A
.equ OCF1B = 2 ; Output Compare Flag 1B
.equ ICF1 = 5 ; Input Capture Flag 1
; TCCR1A - Timer/Counter1 Control Register A
.equ WGM10 = 0 ; Waveform Generation Mode
.equ WGM11 = 1 ; Waveform Generation Mode
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
.equ WGM12 = 3 ; Waveform Generation Mode
.equ WGM13 = 4 ; Waveform Generation Mode
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
; TCCR1C - Timer/Counter 1 Control Register C
.equ FOC1B = 6 ; Force Output Compare 1B
.equ FOC1A = 7 ; Force Output Compare 1A
; ***** TIMER_COUNTER_2 **************
; TIMSK2 - Timer/Counter2 Interrupt Mask register
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable
; TIFR2 - Timer/Counter2 Interrupt Flag Register
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2
; TCCR2A - Timer/Counter2 Control Register
.equ CS20 = 0 ; Clock Select bit 0
.equ CS21 = 1 ; Clock Select bit 1
.equ CS22 = 2 ; Clock Select bit 2
.equ WGM21 = 3 ; Waveform Generation Mode
.equ COM2A0 = 4 ; Compare Output Mode bit 0
.equ COM2A1 = 5 ; Compare Output Mode bit 1
.equ WGM20 = 6 ; Waveform Generation Mode
.equ FOC2A = 7 ; Force Output Compare A
; TCNT2 - Timer/Counter2
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
; OCR2A - Timer/Counter2 Output Compare Register
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
; GTCCR - General Timer/Counter Control Register
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
; ASSR - Asynchronous Status Register
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2
.equ EXCLK = 4 ; Enable External Clock Interrupt
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDTCSR = WDTCR ; For compatibility
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDTOE = WDCE ; For compatibility
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ SPMCR = SPMCSR ; For compatibility
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ BLBSET = 3 ; Boot Lock Bit Set
.equ RWWSRE = 4 ; Read While Write section read enable
.equ ASRE = RWWSRE ; For compatibility
.equ RWWSB = 6 ; Read While Write Section Busy
.equ ASB = RWWSB ; For compatibility
.equ SPMIE = 7 ; SPM Interrupt Enable
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lock bit
.equ LB2 = 1 ; Lock bit
.equ BLB01 = 2 ; Boot Lock bit
.equ BLB02 = 3 ; Boot Lock bit
.equ BLB11 = 4 ; Boot lock bit
.equ BLB12 = 5 ; Boot lock bit
; ***** FUSES ************************************************************
; LOW fuse bits
.equ CKSEL0 = 0 ; Select Clock Source
.equ CKSEL1 = 1 ; Select Clock Source
.equ CKSEL2 = 2 ; Select Clock Source
.equ CKSEL3 = 3 ; Select Clock Source
.equ SUT0 = 4 ; Select start-up time
.equ SUT1 = 5 ; Select start-up time
.equ CKOUT = 6 ; Oscillator options
.equ CKDIV8 = 7 ; Divide clock by 8
; HIGH fuse bits
.equ BOOTRST = 0 ; Select Reset Vector
.equ BOOTSZ0 = 1 ; Select Boot Size
.equ BOOTSZ1 = 2 ; Select Boot Size
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
.equ WDTON = 4 ; Watchdog timer always on
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
.equ JTAGEN = 6 ; Enable JTAG
.equ OCDEN = 7 ; Enable OCD
; EXTENDED fuse bits
.equ RESERVED = 0 ; Reserved fuse bit, do not program
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x7fff ; Note: Word address
.equ IOEND = 0x00ff
.equ SRAM_START = 0x0100
.equ SRAM_SIZE = 4096
.equ RAMEND = 0x10ff
.equ XRAMEND = 0x0000
.equ E2END = 0x07ff
.equ EEPROMEND = 0x07ff
.equ EEADRBITS = 11
#pragma AVRPART MEMORY PROG_FLASH 65536
#pragma AVRPART MEMORY EEPROM 2048
#pragma AVRPART MEMORY INT_SRAM SIZE 4096
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
; ***** BOOTLOADER DECLARATIONS ******************************************
.equ NRWW_START_ADDR = 0x7000
.equ NRWW_STOP_ADDR = 0x7fff
.equ RWW_START_ADDR = 0x0
.equ RWW_STOP_ADDR = 0x6fff
.equ PAGESIZE = 128
.equ FIRSTBOOTSTART = 0x7e00
.equ SECONDBOOTSTART = 0x7c00
.equ THIRDBOOTSTART = 0x7800
.equ FOURTHBOOTSTART = 0x7000
.equ SMALLBOOTSTART = FIRSTBOOTSTART
.equ LARGEBOOTSTART = FOURTHBOOTSTART
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0002 ; External Interrupt Request 0
.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0
.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete
.equ URXC0addr = 0x001a ; USART0, Rx Complete
.equ URXCaddr = 0x001a ; For compatibility
.equ UDRE0addr = 0x001c ; USART0 Data register Empty
.equ UDREaddr = 0x001c ; For compatibility
.equ UTXC0addr = 0x001e ; USART0, Tx Complete
.equ UTXCaddr = 0x001e ; For compatibility
.equ USI_STARTaddr = 0x0020 ; USI Start Condition
.equ USI_OVFaddr = 0x0022 ; USI Overflow
.equ ACIaddr = 0x0024 ; Analog Comparator
.equ ADCCaddr = 0x0026 ; ADC Conversion Complete
.equ ERDYaddr = 0x0028 ; EEPROM Ready
.equ SPMRaddr = 0x002a ; Store Program Memory Read
.equ LCDSFaddr = 0x002c ; LCD Start of Frame
.equ INT_VECTORS_SIZE = 46 ; size in words
#endif /* _M649DEF_INC_ */
; ***** END OF FILE ******************************************************
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