?? m169def.inc
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2007-12-13 07:27 ******* Source: ATmega169.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m169def.inc"
;* Title : Register/Bit Definitions for the ATmega169
;* Date : 2007-12-13
;* Version : 2.24
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega169
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _M169DEF_INC_
#define _M169DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATmega169
#pragma AVRPART ADMIN PART_NAME ATmega169
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x94
.equ SIGNATURE_002 = 0x05
#pragma AVRPART CORE CORE_VERSION V2E
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ LCDDR18 = 0xfe ; MEMORY MAPPED
.equ LCDDR17 = 0xfd ; MEMORY MAPPED
.equ LCDDR16 = 0xfc ; MEMORY MAPPED
.equ LCDDR15 = 0xfb ; MEMORY MAPPED
.equ LCDDR13 = 0xf9 ; MEMORY MAPPED
.equ LCDDR12 = 0xf8 ; MEMORY MAPPED
.equ LCDDR11 = 0xf7 ; MEMORY MAPPED
.equ LCDDR10 = 0xf6 ; MEMORY MAPPED
.equ LCDDR8 = 0xf4 ; MEMORY MAPPED
.equ LCDDR7 = 0xf3 ; MEMORY MAPPED
.equ LCDDR6 = 0xf2 ; MEMORY MAPPED
.equ LCDDR5 = 0xf1 ; MEMORY MAPPED
.equ LCDDR3 = 0xef ; MEMORY MAPPED
.equ LCDDR2 = 0xee ; MEMORY MAPPED
.equ LCDDR1 = 0xed ; MEMORY MAPPED
.equ LCDDR0 = 0xec ; MEMORY MAPPED
.equ LCDCCR = 0xe7 ; MEMORY MAPPED
.equ LCDFRR = 0xe6 ; MEMORY MAPPED
.equ LCDCRB = 0xe5 ; MEMORY MAPPED
.equ LCDCRA = 0xe4 ; MEMORY MAPPED
.equ UDR0 = 0xc6 ; MEMORY MAPPED
.equ UBRR0L = 0xc4 ; MEMORY MAPPED
.equ UBRR0H = 0xc5 ; MEMORY MAPPED
.equ UCSR0C = 0xc2 ; MEMORY MAPPED
.equ UCSR0B = 0xc1 ; MEMORY MAPPED
.equ UCSR0A = 0xc0 ; MEMORY MAPPED
.equ USIDR = 0xba ; MEMORY MAPPED
.equ USISR = 0xb9 ; MEMORY MAPPED
.equ USICR = 0xb8 ; MEMORY MAPPED
.equ ASSR = 0xb6 ; MEMORY MAPPED
.equ OCR2A = 0xb3 ; MEMORY MAPPED
.equ TCNT2 = 0xb2 ; MEMORY MAPPED
.equ TCCR2B = 0xb1 ; MEMORY MAPPED
.equ TCCR2A = 0xb0 ; MEMORY MAPPED
.equ OCR1BL = 0x8a ; MEMORY MAPPED
.equ OCR1BH = 0x8b ; MEMORY MAPPED
.equ OCR1AL = 0x88 ; MEMORY MAPPED
.equ OCR1AH = 0x89 ; MEMORY MAPPED
.equ ICR1L = 0x86 ; MEMORY MAPPED
.equ ICR1H = 0x87 ; MEMORY MAPPED
.equ TCNT1L = 0x84 ; MEMORY MAPPED
.equ TCNT1H = 0x85 ; MEMORY MAPPED
.equ TCCR1C = 0x82 ; MEMORY MAPPED
.equ TCCR1B = 0x81 ; MEMORY MAPPED
.equ TCCR1A = 0x80 ; MEMORY MAPPED
.equ DIDR1 = 0x7f ; MEMORY MAPPED
.equ DIDR0 = 0x7e ; MEMORY MAPPED
.equ ADMUX = 0x7c ; MEMORY MAPPED
.equ ADCSRB = 0x7b ; MEMORY MAPPED
.equ ADCSRA = 0x7a ; MEMORY MAPPED
.equ ADCH = 0x79 ; MEMORY MAPPED
.equ ADCL = 0x78 ; MEMORY MAPPED
.equ TIMSK2 = 0x70 ; MEMORY MAPPED
.equ TIMSK1 = 0x6f ; MEMORY MAPPED
.equ TIMSK0 = 0x6e ; MEMORY MAPPED
.equ PCMSK0 = 0x6b ; MEMORY MAPPED
.equ PCMSK1 = 0x6c ; MEMORY MAPPED
.equ EICRA = 0x69 ; MEMORY MAPPED
.equ OSCCAL = 0x66 ; MEMORY MAPPED
.equ PRR = 0x64 ; MEMORY MAPPED
.equ CLKPR = 0x61 ; MEMORY MAPPED
.equ WDTCR = 0x60 ; MEMORY MAPPED
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ SPMCSR = 0x37
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ SMCR = 0x33
.equ OCDR = 0x31
.equ ACSR = 0x30
.equ SPDR = 0x2e
.equ SPSR = 0x2d
.equ SPCR = 0x2c
.equ GPIOR2 = 0x2b
.equ GPIOR1 = 0x2a
.equ OCR0A = 0x27
.equ TCNT0 = 0x26
.equ TCCR0A = 0x24
.equ GTCCR = 0x23
.equ EEARL = 0x21
.equ EEARH = 0x22
.equ EEDR = 0x20
.equ EECR = 0x1f
.equ GPIOR0 = 0x1e
.equ EIMSK = 0x1d
.equ EIFR = 0x1c
.equ TIFR2 = 0x17
.equ TIFR1 = 0x16
.equ TIFR0 = 0x15
.equ PORTG = 0x14
.equ DDRG = 0x13
.equ PING = 0x12
.equ PORTF = 0x11
.equ DDRF = 0x10
.equ PINF = 0x0f
.equ PORTE = 0x0e
.equ DDRE = 0x0d
.equ PINE = 0x0c
.equ PORTD = 0x0b
.equ DDRD = 0x0a
.equ PIND = 0x09
.equ PORTC = 0x08
.equ DDRC = 0x07
.equ PINC = 0x06
.equ PORTB = 0x05
.equ DDRB = 0x04
.equ PINB = 0x03
.equ PORTA = 0x02
.equ DDRA = 0x01
.equ PINA = 0x00
; ***** BIT DEFINITIONS **************************************************
; ***** TIMER_COUNTER_0 **************
; TCCR0A - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select 0
.equ CS01 = 1 ; Clock Select 1
.equ CS02 = 2 ; Clock Select 2
.equ WGM01 = 3 ; Waveform Generation Mode 1
.equ COM0A0 = 4 ; Compare match Output Mode 0
.equ COM0A1 = 5 ; Compare Match Output Mode 1
.equ WGM00 = 6 ; Waveform Generation Mode 0
.equ FOC0A = 7 ; Force Output Compare
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCR0A0 = 0 ;
.equ OCR0A1 = 1 ;
.equ OCR0A2 = 2 ;
.equ OCR0A3 = 3 ;
.equ OCR0A4 = 4 ;
.equ OCR0A5 = 5 ;
.equ OCR0A6 = 6 ;
.equ OCR0A7 = 7 ;
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable
; TIFR0 - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0
; GTCCR - General Timer/Control Register
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
.equ PSR10 = PSR310 ; For compatibility
.equ PSR0 = PSR310 ; For compatibility
.equ PSR1 = PSR310 ; For compatibility
.equ PSR3 = PSR310 ; For compatibility
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_1 **************
; TIMSK1 - Timer/Counter1 Interrupt Mask Register
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
; TIFR1 - Timer/Counter1 Interrupt Flag register
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
.equ OCF1A = 1 ; Output Compare Flag 1A
.equ OCF1B = 2 ; Output Compare Flag 1B
.equ ICF1 = 5 ; Input Capture Flag 1
; TCCR1A - Timer/Counter1 Control Register A
.equ WGM10 = 0 ; Waveform Generation Mode
.equ WGM11 = 1 ; Waveform Generation Mode
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
.equ WGM12 = 3 ; Waveform Generation Mode
.equ WGM13 = 4 ; Waveform Generation Mode
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
; TCCR1C - Timer/Counter 1 Control Register C
.equ FOC1B = 6 ; Force Output Compare 1B
.equ FOC1A = 7 ; Force Output Compare 1A
; ***** TIMER_COUNTER_2 **************
; TIMSK2 - Timer/Counter2 Interrupt Mask register
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable
; TIFR2 - Timer/Counter2 Interrupt Flag Register
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2
; TCCR2A - Timer/Counter2 Control Register
.equ CS20 = 0 ; Clock Select bit 0
.equ CS21 = 1 ; Clock Select bit 1
.equ CS22 = 2 ; Clock Select bit 2
.equ WGM21 = 3 ; Waveform Generation Mode
.equ COM2A0 = 4 ; Compare Output Mode bit 0
.equ COM2A1 = 5 ; Compare Output Mode bit 1
.equ WGM20 = 6 ; Waveform Generation Mode
.equ FOC2A = 7 ; Force Output Compare A
; TCNT2 - Timer/Counter2
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
; OCR2A - Timer/Counter2 Output Compare Register
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
; GTCCR - General Timer/Counter Control Register
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
; ASSR - Asynchronous Status Register
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2
.equ EXCLK = 4 ; Enable External Clock Interrupt
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDTCSR = WDTCR ; For compatibility
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDTOE = WDCE ; For compatibility
; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
.equ EEWEE = EEMWE ; For compatibility
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
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