?? m16hvadef.inc
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2007-12-13 07:27 ******* Source: ATmega16HVA.xml *********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m16HVAdef.inc"
;* Title : Register/Bit Definitions for the ATmega16HVA
;* Date : 2007-12-13
;* Version : 2.24
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega16HVA
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _M16HVADEF_INC_
#define _M16HVADEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATmega16HVA
#pragma AVRPART ADMIN PART_NAME ATmega16HVA
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x94
.equ SIGNATURE_002 = 0x0c
#pragma AVRPART CORE CORE_VERSION V2E
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ BPPLR = 0xfe ; MEMORY MAPPED
.equ BPCR = 0xfd ; MEMORY MAPPED
.equ BPHCTR = 0xfc ; MEMORY MAPPED
.equ BPOCTR = 0xfb ; MEMORY MAPPED
.equ BPSCTR = 0xfa ; MEMORY MAPPED
.equ BPCHCD = 0xf9 ; MEMORY MAPPED
.equ BPDHCD = 0xf8 ; MEMORY MAPPED
.equ BPCOCD = 0xf7 ; MEMORY MAPPED
.equ BPDOCD = 0xf6 ; MEMORY MAPPED
.equ BPSCD = 0xf5 ; MEMORY MAPPED
.equ BPIFR = 0xf3 ; MEMORY MAPPED
.equ BPIMSK = 0xf2 ; MEMORY MAPPED
.equ FCSR = 0xf0 ; MEMORY MAPPED
.equ CADICL = 0xe8 ; MEMORY MAPPED
.equ CADICH = 0xe9 ; MEMORY MAPPED
.equ CADRC = 0xe6 ; MEMORY MAPPED
.equ CADCSRB = 0xe5 ; MEMORY MAPPED
.equ CADCSRA = 0xe4 ; MEMORY MAPPED
.equ CADAC3 = 0xe3 ; MEMORY MAPPED
.equ CADAC2 = 0xe2 ; MEMORY MAPPED
.equ CADAC1 = 0xe1 ; MEMORY MAPPED
.equ CADAC0 = 0xe0 ; MEMORY MAPPED
.equ BGCRR = 0xd1 ; MEMORY MAPPED
.equ BGCCR = 0xd0 ; MEMORY MAPPED
.equ ROCR = 0xc8 ; MEMORY MAPPED
.equ OCR1B = 0x89 ; MEMORY MAPPED
.equ OCR1A = 0x88 ; MEMORY MAPPED
.equ TCNT1L = 0x84 ; MEMORY MAPPED
.equ TCNT1H = 0x85 ; MEMORY MAPPED
.equ TCCR1B = 0x81 ; MEMORY MAPPED
.equ TCCR1A = 0x80 ; MEMORY MAPPED
.equ DIDR0 = 0x7e ; MEMORY MAPPED
.equ VADMUX = 0x7c ; MEMORY MAPPED
.equ VADCSR = 0x7a ; MEMORY MAPPED
.equ VADCL = 0x78 ; MEMORY MAPPED
.equ TIMSK1 = 0x6f ; MEMORY MAPPED
.equ TIMSK0 = 0x6e ; MEMORY MAPPED
.equ EICRA = 0x69 ; MEMORY MAPPED
.equ FOSCCAL = 0x66 ; MEMORY MAPPED
.equ PRR0 = 0x64 ; MEMORY MAPPED
.equ CLKPR = 0x61 ; MEMORY MAPPED
.equ WDTCSR = 0x60 ; MEMORY MAPPED
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ SPMCSR = 0x37
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ SMCR = 0x33
.equ DWDR = 0x31
.equ SPDR = 0x2e
.equ SPSR = 0x2d
.equ SPCR = 0x2c
.equ GPIOR2 = 0x2b
.equ GPIOR1 = 0x2a
.equ OCR0B = 0x29
.equ OCR0A = 0x28
.equ TCNT0L = 0x26
.equ TCNT0H = 0x27
.equ TCCR0B = 0x25
.equ TCCR0A = 0x24
.equ GTCCR = 0x23
.equ EEAR = 0x21
.equ EEDR = 0x20
.equ EECR = 0x1f
.equ GPIOR0 = 0x1e
.equ EIMSK = 0x1d
.equ EIFR = 0x1c
.equ OSICSR = 0x17
.equ TIFR1 = 0x16
.equ TIFR0 = 0x15
.equ PORTC = 0x08
.equ PINC = 0x06
.equ PORTB = 0x05
.equ DDRB = 0x04
.equ PINB = 0x03
.equ PORTA = 0x02
.equ DDRA = 0x01
.equ PINA = 0x00
; ***** BIT DEFINITIONS **************************************************
; ***** AD_CONVERTER *****************
; VADMUX - The VADC multiplexer Selection Register
.equ VADMUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ VADMUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ VADMUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ VADMUX3 = 3 ; Analog Channel and Gain Selection Bits
; VADCSR - The VADC Control and Status register
.equ VADCCIE = 0 ; VADC Conversion Complete Interrupt Enable
.equ VADCCIF = 1 ; VADC Conversion Complete Interrupt Flag
.equ VADSC = 2 ; VADC Satrt Conversion
.equ VADEN = 3 ; VADC Enable
; ***** WATCHDOG *********************
; WDTCSR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
; ***** BANDGAP **********************
; BGCRR - Bandgap Calibration of Resistor Ladder
.equ BGCR0 = 0 ; Bandgap Calibration of Resistor Ladder Bit 0
.equ BGCR1 = 1 ; Bandgap Calibration of Resistor Ladder Bit 1
.equ BGCR2 = 2 ; Bandgap Calibration of Resistor Ladder Bit 2
.equ BGCR3 = 3 ; Bandgap Calibration of Resistor Ladder Bit 3
.equ BGCR4 = 4 ; Bandgap Calibration of Resistor Ladder Bit 4
.equ BGCR5 = 5 ; Bandgap Calibration of Resistor Ladder Bit 5
.equ BGCR6 = 6 ; Bandgap Calibration of Resistor Ladder Bit 6
.equ BGCR7 = 7 ; Bandgap Calibration of Resistor Ladder Bit 7
; BGCCR - Bandgap Calibration Register
.equ BGCC0 = 0 ; BG Calibration of PTAT Current Bit 0
.equ BGCC1 = 1 ; BG Calibration of PTAT Current Bit 1
.equ BGCC2 = 2 ; BG Calibration of PTAT Current Bit 2
.equ BGCC3 = 3 ; BG Calibration of PTAT Current Bit 3
.equ BGCC4 = 4 ; BG Calibration of PTAT Current Bit 4
.equ BGCC5 = 5 ; BG Calibration of PTAT Current Bit 5
.equ BGD = 7 ; Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.
; ***** EXTERNAL_INTERRUPT ***********
; EICRA - External Interrupt Control Register
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1
.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0
.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1
.equ ISC20 = 4 ; External Interrupt Sense Control 2 Bit 0
.equ ISC21 = 5 ; External Interrupt Sense Control 2 Bit 1
; EIMSK - External Interrupt Mask Register
.equ INT0 = 0 ; External Interrupt Request 0 Enable
.equ INT1 = 1 ; External Interrupt Request 1 Enable
.equ INT2 = 2 ; External Interrupt Request 2 Enable
; EIFR - External Interrupt Flag Register
.equ INTF0 = 0 ; External Interrupt Flag 0
.equ INTF1 = 1 ; External Interrupt Flag 1
.equ INTF2 = 2 ; External Interrupt Flag 2
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input pin 0
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
; ***** FET **************************
; FCSR - FET Control and Status Register
.equ CFE = 0 ; Charge FET Enable
.equ DFE = 1 ; Discharge FET Enable
.equ CPS = 2 ; Current Protection Status
.equ DUVRD = 3 ; Deep Under-Voltage Recovery Disable
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control and Status Register
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ RFLB = 3 ; Read Fuse and Lock Bits
.equ CTPB = 4 ; Clear Temporary Page Buffer
.equ SIGRD = 5 ; Signature Row Read
; ***** PORTB ************************
; PORTB - Data Register, Port B
.equ PORTB0 = 0 ;
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ;
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ;
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ;
.equ PB3 = 3 ; For compatibility
; DDRB - Data Direction Register, Port B
.equ DDB0 = 0 ;
.equ DDB1 = 1 ;
.equ DDB2 = 2 ;
.equ DDB3 = 3 ;
; PINB - Input Pins, Port B
.equ PINB0 = 0 ;
.equ PINB1 = 1 ;
.equ PINB2 = 2 ;
.equ PINB3 = 3 ;
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
; MCUCR - MCU Control Register
.equ PUD = 4 ; Pull-up disable
.equ CKOE = 5 ; Clock Output Enable
; MCUSR - MCU Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ BODRF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
.equ OCDRF = 4 ; OCD Reset Flag
; FOSCCAL - Fast Oscillator Calibration Value
.equ FCAL0 = 0 ; Oscillator Calibration Value Bit0
.equ FCAL1 = 1 ; Oscillator Calibration Value Bit1
.equ FCAL3 = 3 ; Oscillator Calibration Value Bit3
.equ FCAL4 = 4 ; Oscillator Calibration Value Bit4
.equ FCAL5 = 5 ; Oscillator Calibration Value Bit5
.equ FCAL6 = 6 ; Oscillator Calibration Value Bit6
.equ FCAL7 = 7 ; Oscillator Calibration Value Bit7
; OSICSR - Oscillator Sampling Interface Control and Status Register
.equ OSIEN = 0 ; Oscillator Sampling Interface Enable
.equ OSIST = 1 ; Oscillator Sampling Interface Status
.equ OSISEL0 = 4 ; Oscillator Sampling Interface Select 0
; SMCR - Sleep Mode Control Register
.equ SE = 0 ; Sleep Enable
.equ SM0 = 1 ; Sleep Mode Select bit 0
.equ SM1 = 2 ; Sleep Mode Select bit 1
.equ SM2 = 3 ; Sleep Mode Select bit 2
; GPIOR2 - General Purpose IO Register 2
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
; GPIOR1 - General Purpose IO Register 1
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
; GPIOR0 - General Purpose IO Register 0
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
; DIDR0 - Digital Input Disable Register
.equ PA0DID = 0 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
.equ PA1DID = 1 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
; PRR0 - Power Reduction Register 0
.equ PRVADC = 0 ; Power Reduction V-ADC
.equ PRTIM0 = 1 ; Power Reduction Timer/Counter0
.equ PRTIM1 = 2 ; Power Reduction Timer/Counter1
.equ PRSPI = 3 ; Power reduction SPI
.equ PRVRM = 5 ; Power Reduction Voltage Regulator Monitor
; CLKPR - Clock Prescale Register
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
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