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; ***** BATTERY_PROTECTION ***********
; BPPLR - Battery Protection Parameter Lock Register
.equ BPPL = 0 ; Battery Protection Parameter Lock
.equ BPPLE = 1 ; Battery Protection Parameter Lock Enable
; BPCR - Battery Protection Control Register
.equ CHCD = 0 ; Charge High-current Protection Disable
.equ DHCD = 1 ; Discharge High-current Protection Disable
.equ COCD = 2 ; Charge Over-current Protection Disabled
.equ DOCD = 3 ; Discharge Over-current Protection Disabled
.equ SCD = 4 ; Short Circuit Protection Disabled
; BPHCTR - Battery Protection Short-current Timing Register
.equ HCPT0 = 0 ; High-current Protection Timing bit 0
.equ HCPT1 = 1 ; High-current Protection Timing bit 1
.equ HCPT2 = 2 ; High-current Protection Timing bit 2
.equ HCPT3 = 3 ; High-current Protection Timing bit 3
.equ HCPT4 = 4 ; High-current Protection Timing bit 4
.equ HCPT5 = 5 ; High-current Protection Timing bit 5
; BPOCTR - Battery Protection Over-current Timing Register
.equ OCPT0 = 0 ; Over-current Protection Timing bit 0
.equ OCPT1 = 1 ; Over-current Protection Timing bit 1
.equ OCPT2 = 2 ; Over-current Protection Timing bit 2
.equ OCPT3 = 3 ; Over-current Protection Timing bit 3
.equ OCPT4 = 4 ; Over-current Protection Timing bit 4
.equ OCPT5 = 5 ; Over-current Protection Timing bit 5
; BPSCTR - Battery Protection Short-current Timing Register
.equ SCPT0 = 0 ; Short-current Protection Timing
.equ SCPT1 = 1 ; Short-current Protection Timing
.equ SCPT2 = 2 ; Short-current Protection Timing
.equ SCPT3 = 3 ; Short-current Protection Timing
.equ SCPT4 = 4 ; Short-current Protection Timing
.equ SCPT5 = 5 ; Short-current Protection Timing
.equ SCPT6 = 6 ; Short-current Protection Timing
; BPCHCD - Battery Protection Charge-High-current Detection Level Register
.equ CHCDL0 = 0 ; Charge High-current Detection Level
.equ CHCDL1 = 1 ; Charge High-current Detection Level
.equ CHCDL2 = 2 ; Charge High-current Detection Level
.equ CHCDL3 = 3 ; Charge High-current Detection Level
.equ CHCDL4 = 4 ; Charge High-current Detection Level
.equ CHCDL5 = 5 ; Charge High-current Detection Level
.equ CHCDL6 = 6 ; Charge High-current Detection Level
.equ CHCDL7 = 7 ; Charge High-current Detection Level
; BPDHCD - Battery Protection Discharge-High-current Detection Level Register
.equ DHCDL0 = 0 ; Discharge High-current Detection Level bit 0
.equ DHCDL1 = 1 ; Discharge High-current Detection Level bit 1
.equ DHCDL2 = 2 ; Discharge High-current Detection Level bit 2
.equ DHCDL3 = 3 ; Discharge High-current Detection Level bit 3
.equ DHCDL4 = 4 ; Discharge High-current Detection Level bit 4
.equ DHCDL5 = 5 ; Discharge High-current Detection Level bit 5
.equ DHCDL6 = 6 ; Discharge High-current Detection Level bit 6
.equ DHCDL7 = 7 ; Discharge High-current Detection Level bit 7
; BPCOCD - Battery Protection Charge-Over-current Detection Level Register
.equ COCDL0 = 0 ; Charge Over-current Detection Level
.equ COCDL1 = 1 ; Charge Over-current Detection Level
.equ COCDL2 = 2 ; Charge Over-current Detection Level
.equ COCDL3 = 3 ; Charge Over-current Detection Level
.equ COCDL4 = 4 ; Charge Over-current Detection Level
.equ COCDL5 = 5 ; Charge Over-current Detection Level
.equ COCDL6 = 6 ; Charge Over-current Detection Level
.equ COCDL7 = 7 ; Charge Over-current Detection Level
; BPDOCD - Battery Protection Discharge-Over-current Detection Level Register
.equ DOCDL0 = 0 ; Discharge Over-current Detection Level bit0
.equ DOCDL1 = 1 ; Discharge Over-current Detection Level bit1
.equ DOCDL2 = 2 ; Discharge Over-current Detection Level bit2
.equ DOCDL3 = 3 ; Discharge Over-current Detection Level bit3
.equ DOCDL4 = 4 ; Discharge Over-current Detection Level bit4
.equ DOCDL5 = 5 ; Discharge Over-current Detection Level bit5
.equ DOCDL6 = 6 ; Discharge Over-current Detection Level bit6
.equ DOCDL7 = 7 ; Discharge Over-current Detection Level bit7
; BPSCD - Battery Protection Short-Circuit Detection Level Register
.equ SCDL0 = 0 ; Short-circuit Detection Level bit 0
.equ SCDL1 = 1 ; Short-circuit Detection Level bit 1
.equ SCDL2 = 2 ; Short-circuit Detection Level bit 2
.equ SCDL3 = 3 ; Short-circuit Detection Level bit 3
.equ SCDL4 = 4 ; Short-circuit Detection Level bit 4
.equ SCDL5 = 5 ; Short-circuit Detection Level bit 5
.equ SCDL6 = 6 ; Short-circuit Detection Level bit 6
.equ SCDL7 = 7 ; Short-circuit Detection Level bit 7
; BPIFR - Battery Protection Interrupt Flag Register
.equ CHCIF = 0 ; Charge High-current Protection Activated Interrupt
.equ DHCIF = 1 ; Disharge High-current Protection Activated Interrupt
.equ COCIF = 2 ; Charge Over-current Protection Activated Interrupt Flag
.equ DOCIF = 3 ; Discharge Over-current Protection Activated Interrupt Flag
.equ SCIF = 4 ; Short-circuit Protection Activated Interrupt Flag
; BPIMSK - Battery Protection Interrupt Mask Register
.equ CHCIE = 0 ; Charger High-current Protection Activated Interrupt
.equ DHCIE = 1 ; Discharger High-current Protection Activated Interrupt
.equ COCIE = 2 ; Charge Over-current Protection Activated Interrupt Enable
.equ DOCIE = 3 ; Discharge Over-current Protection Activated Interrupt Enable
.equ SCIE = 4 ; Short-circuit Protection Activated Interrupt Enable
; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ EEARL = EEAR ; For compatibility
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
.equ EEAR7 = 7 ; EEPROM Read/Write Access bit 7
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEPE = 1 ; EEPROM Write Enable
.equ EEWE = EEPE ; For compatibility
.equ EEMPE = 2 ; EEPROM Master Write Enable
.equ EEMWE = EEMPE ; For compatibility
.equ EERIE = 3 ; EEProm Ready Interrupt Enable
.equ EEPM0 = 4 ;
.equ EEPM1 = 5 ;
; ***** TIMER_COUNTER_1 **************
; TCCR1A - Timer/Counter 1 Control Register A
.equ WGM10 = 0 ; Waveform Generation Mode
.equ ICS1 = 3 ; Input Capture Select
.equ ICES1 = 4 ; Input Capture Edge Select
.equ ICNC1 = 5 ; Input Capture Noise Canceler
.equ ICEN1 = 6 ; Input Capture Mode Enable
.equ TCW1 = 7 ; Timer/Counter Width
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select1 bit 0
.equ CS11 = 1 ; Clock Select1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
; OCR1A - Output Compare Register 1A
.equ OCR1A0 = 0 ;
.equ OCR1A1 = 1 ;
.equ OCR1A2 = 2 ;
.equ OCR1A3 = 3 ;
.equ OCR1A4 = 4 ;
.equ OCR1A5 = 5 ;
.equ OCR1A6 = 6 ;
.equ OCR1A7 = 7 ;
; OCR1B - Output Compare Register B
.equ OCR1B0 = 0 ;
.equ OCR1B1 = 1 ;
.equ OCR1B2 = 2 ;
.equ OCR1B3 = 3 ;
.equ OCR1B4 = 4 ;
.equ OCR1B5 = 5 ;
.equ OCR1B6 = 6 ;
.equ OCR1B7 = 7 ;
; TIMSK1 - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Interrupt Enable
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Interrupt Enable
.equ ICIE1 = 3 ; Timer/Counter n Input Capture Interrupt Enable
; TIFR1 - Timer/Counter Interrupt Flag register
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
.equ OCF1A = 1 ; Timer/Counter1 Output Compare Flag A
.equ OCF1B = 2 ; Timer/Counter1 Output Compare Flag B
.equ ICF1 = 3 ; Timer/Counter 1 Input Capture Flag
; GTCCR - General Timer/Counter Control Register
.equ PSRSYNC = 0 ; Prescaler Reset
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** COULOMB_COUNTER **************
; CADCSRA - CC-ADC Control and Status Register A
.equ CADSE = 0 ; When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
.equ CADSI0 = 1 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
.equ CADSI1 = 2 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
.equ CADAS0 = 3 ; CC_ADC Accumulate Current Select Bit 0
.equ CADAS1 = 4 ; CC_ADC Accumulate Current Select Bit 1
.equ CADUB = 5 ; CC_ADC Update Busy
.equ CADPOL = 6 ;
.equ CADEN = 7 ; When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
; CADCSRB - CC-ADC Control and Status Register B
.equ CADICIF = 0 ; CC-ADC Instantaneous Current Interrupt Flag
.equ CADRCIF = 1 ; CC-ADC Accumulate Current Interrupt Flag
.equ CADACIF = 2 ; CC-ADC Accumulate Current Interrupt Flag
.equ CADICIE = 4 ; CAD Instantenous Current Interrupt Enable
.equ CADRCIE = 5 ; Regular Current Interrupt Enable
.equ CADACIE = 6 ;
; CADAC3 - ADC Accumulate Current
.equ CADAC24 = 0 ;
.equ CADAC25 = 1 ;
.equ CADAC26 = 2 ;
.equ CADAC27 = 3 ;
.equ CADAC28 = 4 ;
.equ CADAC29 = 5 ;
.equ CADAC30 = 6 ;
.equ CADAC31 = 7 ;
; CADAC2 - ADC Accumulate Current
.equ CADAC16 = 0 ;
.equ CADAC17 = 1 ;
.equ CADAC18 = 2 ;
.equ CADAC19 = 3 ;
.equ CADAC20 = 4 ;
.equ CADAC21 = 5 ;
.equ CADAC22 = 6 ;
.equ CADAC23 = 7 ;
; CADAC1 - ADC Accumulate Current
.equ CADAC08 = 0 ;
.equ CADAC09 = 1 ;
.equ CADAC10 = 2 ;
.equ CADAC11 = 3 ;
.equ CADAC12 = 4 ;
.equ CADAC13 = 5 ;
.equ CADAC14 = 6 ;
.equ CADAC15 = 7 ;
; CADAC0 - ADC Accumulate Current
.equ CADAC00 = 0 ;
.equ CADAC01 = 1 ;
.equ CADAC02 = 2 ;
.equ CADAC03 = 3 ;
.equ CADAC04 = 4 ;
.equ CADAC05 = 5 ;
.equ CADAC06 = 6 ;
.equ CADAC07 = 7 ;
; CADRC - CC-ADC Regular Current
.equ CADRC0 = 0 ;
.equ CADRC1 = 1 ;
.equ CADRC2 = 2 ;
.equ CADRC3 = 3 ;
.equ CADRC4 = 4 ;
.equ CADRC5 = 5 ;
.equ CADRC6 = 6 ;
.equ CADRC7 = 7 ;
; ***** TIMER_COUNTER_0 **************
; TCCR0A - Timer/Counter0 Control Register
.equ WGM00 = 0 ; Clock Select0 bit 0
.equ ICS0 = 3 ; Input Capture Select
.equ ICES0 = 4 ; Input Capture Edge Select
.equ ICNC0 = 5 ; Input Capture Noise Canceler
.equ ICEN0 = 6 ; Input Capture Mode Enable
.equ TCW0 = 7 ; Timer/Counter Width
; TCCR0B - Timer/Counter0 Control Register
.equ CS00 = 0 ; Clock Select0 bit 0
.equ CS01 = 1 ; Clock Select0 bit 1
.equ CS02 = 2 ; Clock Select0 bit 2
; OCR0A - Output compare Register A
.equ OCR0A0 = 0 ;
.equ OCR0A1 = 1 ;
.equ OCR0A2 = 2 ;
.equ OCR0A3 = 3 ;
.equ OCR0A4 = 4 ;
.equ OCR0A5 = 5 ;
.equ OCR0A6 = 6 ;
.equ OCR0A7 = 7 ;
; OCR0B - Output compare Register B
.equ OCR0B0 = 0 ;
.equ OCR0B1 = 1 ;
.equ OCR0B2 = 2 ;
.equ OCR0B3 = 3 ;
.equ OCR0B4 = 4 ;
.equ OCR0B5 = 5 ;
.equ OCR0B6 = 6 ;
.equ OCR0B7 = 7 ;
; TIMSK0 - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 0 ; Overflow Interrupt Enable
.equ OCIE0A = 1 ; Output Compare Interrupt Enable
.equ OCIE0B = 2 ; Output Compare Interrupt Enable
.equ ICIE0 = 3 ; Timer/Counter n Input Capture Interrupt Enable
; TIFR0 - Timer/Counter Interrupt Flag register
.equ TOV0 = 0 ; Overflow Flag
.equ OCF0A = 1 ; Output Compare Flag
.equ OCF0B = 2 ; Output Compare Flag
.equ ICF0 = 3 ; Timer/Counter Interrupt Flag Register
; ***** VOLTAGE_REGULATOR ************
; ROCR - Regulator Operating Condition Register
.equ ROCWIE = 0 ; ROC Warning Interrupt Enable
.equ ROCWIF = 1 ; ROC Warning Interrupt Flag
.equ ROCS = 7 ; ROC Status
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
; ***** FUSES ************************************************************
; LOW fuse bits
.equ SUT0 = 0 ; Select start-up time
.equ SUT1 = 1 ; Select start-up time
.equ SUT2 = 2 ; Select start-up time
.equ SELFPRGEN = 3 ; Enable self programming
.equ DWEN = 4 ; Enable debugWIRE
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
.equ EESAVE = 6 ; EEPROM memory is preserved through chip erase
.equ WDTON = 7 ; Watchdog Timer Always On
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x1fff ; Note: Word address
.equ IOEND = 0x00ff
.equ SRAM_START = 0x0100
.equ SRAM_SIZE = 512
.equ RAMEND = 0x02ff
.equ XRAMEND = 0x0000
.equ E2END = 0x00ff
.equ EEPROMEND = 0x00ff
.equ EEADRBITS = 8
#pragma AVRPART MEMORY PROG_FLASH 16384
#pragma AVRPART MEMORY EEPROM 256
#pragma AVRPART MEMORY INT_SRAM SIZE 512
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
; ***** BOOTLOADER DECLARATIONS ******************************************
.equ NRWW_START_ADDR = 0x0
.equ NRWW_STOP_ADDR = 0x0
.equ RWW_START_ADDR = 0x0
.equ RWW_STOP_ADDR = 0x0
.equ PAGESIZE = 64
; ***** INTERRUPT VECTORS ************************************************
.equ BPINTaddr = 0x0002 ; Battery Protection Interrupt
.equ VREGMONaddr = 0x0004 ; Voltage regulator monitor interrupt
.equ INT0addr = 0x0006 ; External Interrupt Request 0
.equ INT1addr = 0x0008 ; External Interrupt Request 1
.equ INT2addr = 0x000a ; External Interrupt Request 2
.equ WDTaddr = 0x000c ; Watchdog Timeout Interrupt
.equ TIMER1_ICaddr = 0x000e ; Timer 1 Input capture
.equ OC1Aaddr = 0x0010 ; Timer 1 Compare Match A
.equ OC1Baddr = 0x0012 ; Timer 1 Compare Match B
.equ OVF1addr = 0x0014 ; Timer 1 overflow
.equ TIMER0_ICaddr = 0x0016 ; Timer 0 Input Capture
.equ OC0Aaddr = 0x0018 ; Timer 0 Comapre Match A
.equ OC0Baddr = 0x001a ; Timer 0 Compare Match B
.equ OVF0addr = 0x001c ; Timer 0 Overflow
.equ SPIaddr = 0x001e ; SPI Serial transfer complete
.equ VADCaddr = 0x0020 ; Voltage ADC Conversion Complete
.equ CADICaddr = 0x0022 ; Coulomb Counter ADC Conversion Complete
.equ CADRCaddr = 0x0024 ; Coloumb Counter ADC Regular Current
.equ CADACaddr = 0x0026 ; Coloumb Counter ADC Accumulator
.equ ERDYaddr = 0x0028 ; EEPROM Ready
.equ INT_VECTORS_SIZE = 42 ; size in words
#endif /* _M16HVADEF_INC_ */
; ***** END OF FILE ******************************************************
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