?? m64def.inc
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2007-12-13 07:27 ******* Source: ATmega64.xml ************
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m64def.inc"
;* Title : Register/Bit Definitions for the ATmega64
;* Date : 2007-12-13
;* Version : 2.24
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega64
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _M64DEF_INC_
#define _M64DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATmega64
#pragma AVRPART ADMIN PART_NAME ATmega64
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x96
.equ SIGNATURE_002 = 0x02
#pragma AVRPART CORE CORE_VERSION V2E
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ UCSR1C = 0x9d ; MEMORY MAPPED
.equ UDR1 = 0x9c ; MEMORY MAPPED
.equ UCSR1A = 0x9b ; MEMORY MAPPED
.equ UCSR1B = 0x9a ; MEMORY MAPPED
.equ UBRR1H = 0x98 ; MEMORY MAPPED
.equ UBRR1L = 0x99 ; MEMORY MAPPED
.equ UCSR0C = 0x95 ; MEMORY MAPPED
.equ UBRR0H = 0x90 ; MEMORY MAPPED
.equ ADCSRB = 0x8e ; MEMORY MAPPED
.equ TCCR3C = 0x8c ; MEMORY MAPPED
.equ TCCR3A = 0x8b ; MEMORY MAPPED
.equ TCCR3B = 0x8a ; MEMORY MAPPED
.equ TCNT3L = 0x88 ; MEMORY MAPPED
.equ TCNT3H = 0x89 ; MEMORY MAPPED
.equ OCR3AL = 0x86 ; MEMORY MAPPED
.equ OCR3AH = 0x87 ; MEMORY MAPPED
.equ OCR3BL = 0x84 ; MEMORY MAPPED
.equ OCR3BH = 0x85 ; MEMORY MAPPED
.equ OCR3CL = 0x82 ; MEMORY MAPPED
.equ OCR3CH = 0x83 ; MEMORY MAPPED
.equ ICR3L = 0x80 ; MEMORY MAPPED
.equ ICR3H = 0x81 ; MEMORY MAPPED
.equ ETIMSK = 0x7d ; MEMORY MAPPED
.equ ETIFR = 0x7c ; MEMORY MAPPED
.equ TCCR1C = 0x7a ; MEMORY MAPPED
.equ OCR1CL = 0x78 ; MEMORY MAPPED
.equ OCR1CH = 0x79 ; MEMORY MAPPED
.equ TWCR = 0x74 ; MEMORY MAPPED
.equ TWDR = 0x73 ; MEMORY MAPPED
.equ TWAR = 0x72 ; MEMORY MAPPED
.equ TWSR = 0x71 ; MEMORY MAPPED
.equ TWBR = 0x70 ; MEMORY MAPPED
.equ OSCCAL = 0x6f ; MEMORY MAPPED
.equ XMCRA = 0x6d ; MEMORY MAPPED
.equ XMCRB = 0x6c ; MEMORY MAPPED
.equ EICRA = 0x6a ; MEMORY MAPPED
.equ SPMCSR = 0x68 ; MEMORY MAPPED
.equ PORTG = 0x65 ; MEMORY MAPPED
.equ DDRG = 0x64 ; MEMORY MAPPED
.equ PING = 0x63 ; MEMORY MAPPED
.equ PORTF = 0x62 ; MEMORY MAPPED
.equ DDRF = 0x61 ; MEMORY MAPPED
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ XDIV = 0x3c
.equ EICRB = 0x3a
.equ EIMSK = 0x39
.equ EIFR = 0x38
.equ TIMSK = 0x37
.equ TIFR = 0x36
.equ MCUCR = 0x35
.equ MCUCSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ OCR0 = 0x31
.equ ASSR = 0x30
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1L = 0x2c
.equ TCNT1H = 0x2d
.equ OCR1AL = 0x2a
.equ OCR1AH = 0x2b
.equ OCR1BL = 0x28
.equ OCR1BH = 0x29
.equ ICR1L = 0x26
.equ ICR1H = 0x27
.equ TCCR2 = 0x25
.equ TCNT2 = 0x24
.equ OCR2 = 0x23
.equ OCDR = 0x22
.equ WDTCR = 0x21
.equ SFIOR = 0x20
.equ EEARL = 0x1e
.equ EEARH = 0x1f
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTA = 0x1b
.equ DDRA = 0x1a
.equ PINA = 0x19
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ DDRC = 0x14
.equ PINC = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR0 = 0x0c
.equ UCSR0A = 0x0b
.equ UCSR0B = 0x0a
.equ UBRR0L = 0x09
.equ ACSR = 0x08
.equ ADMUX = 0x07
.equ ADCSRA = 0x06
.equ ADCH = 0x05
.equ ADCL = 0x04
.equ PORTE = 0x03
.equ DDRE = 0x02
.equ PINE = 0x01
.equ PINF = 0x00
; ***** BIT DEFINITIONS **************************************************
; ***** ANALOG_COMPARATOR ************
; SFIOR - Special Function IO Register
.equ ACME = 3 ; Analog Comparator Multiplexer Enable
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Compare Output
.equ ACBG = 6 ; Analog Comparator Bandgap Select
.equ ACD = 7 ; Analog Comparator Disable
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
.equ ADLAR = 5 ; Left Adjust Result
.equ REFS0 = 6 ; Reference Selection Bit 0
.equ REFS1 = 7 ; Reference Selection Bit 1
; ADCSRA - The ADC Control and Status register A
.equ ADCSR = ADCSRA ; For compatibility
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADATE = 5 ; ADC Auto Trigger Enable
.equ ADFR = ADATE ; For compatibility
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
; ADCH - ADC Data Register High Byte
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
; ADCL - ADC Data Register Low Byte
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
; ADCSRB - The ADC Control and Status register B
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
; ***** TWI **************************
; TWBR - TWI Bit Rate register
.equ I2BR = TWBR ; For compatibility
.equ TWBR0 = 0 ;
.equ TWBR1 = 1 ;
.equ TWBR2 = 2 ;
.equ TWBR3 = 3 ;
.equ TWBR4 = 4 ;
.equ TWBR5 = 5 ;
.equ TWBR6 = 6 ;
.equ TWBR7 = 7 ;
; TWCR - TWI Control Register
.equ I2CR = TWCR ; For compatibility
.equ TWIE = 0 ; TWI Interrupt Enable
.equ I2IE = TWIE ; For compatibility
.equ TWEN = 2 ; TWI Enable Bit
.equ I2EN = TWEN ; For compatibility
.equ ENI2C = TWEN ; For compatibility
.equ TWWC = 3 ; TWI Write Collition Flag
.equ I2WC = TWWC ; For compatibility
.equ TWSTO = 4 ; TWI Stop Condition Bit
.equ I2STO = TWSTO ; For compatibility
.equ TWSTA = 5 ; TWI Start Condition Bit
.equ I2STA = TWSTA ; For compatibility
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
.equ I2EA = TWEA ; For compatibility
.equ TWINT = 7 ; TWI Interrupt Flag
.equ I2INT = TWINT ; For compatibility
; TWSR - TWI Status Register
.equ I2SR = TWSR ; For compatibility
.equ TWPS0 = 0 ; TWI Prescaler
.equ TWS0 = TWPS0 ; For compatibility
.equ I2GCE = TWPS0 ; For compatibility
.equ TWPS1 = 1 ; TWI Prescaler
.equ TWS1 = TWPS1 ; For compatibility
.equ TWS3 = 3 ; TWI Status
.equ I2S3 = TWS3 ; For compatibility
.equ TWS4 = 4 ; TWI Status
.equ I2S4 = TWS4 ; For compatibility
.equ TWS5 = 5 ; TWI Status
.equ I2S5 = TWS5 ; For compatibility
.equ TWS6 = 6 ; TWI Status
.equ I2S6 = TWS6 ; For compatibility
.equ TWS7 = 7 ; TWI Status
.equ I2S7 = TWS7 ; For compatibility
; TWDR - TWI Data register
.equ I2DR = TWDR ; For compatibility
.equ TWD0 = 0 ; TWI Data Register Bit 0
.equ TWD1 = 1 ; TWI Data Register Bit 1
.equ TWD2 = 2 ; TWI Data Register Bit 2
.equ TWD3 = 3 ; TWI Data Register Bit 3
.equ TWD4 = 4 ; TWI Data Register Bit 4
.equ TWD5 = 5 ; TWI Data Register Bit 5
.equ TWD6 = 6 ; TWI Data Register Bit 6
.equ TWD7 = 7 ; TWI Data Register Bit 7
; TWAR - TWI (Slave) Address register
.equ I2AR = TWAR ; For compatibility
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
; ***** USART0 ***********************
; UDR0 - USART I/O Data Register
.equ UDR00 = 0 ; USART I/O Data Register bit 0
.equ UDR01 = 1 ; USART I/O Data Register bit 1
.equ UDR02 = 2 ; USART I/O Data Register bit 2
.equ UDR03 = 3 ; USART I/O Data Register bit 3
.equ UDR04 = 4 ; USART I/O Data Register bit 4
.equ UDR05 = 5 ; USART I/O Data Register bit 5
.equ UDR06 = 6 ; USART I/O Data Register bit 6
.equ UDR07 = 7 ; USART I/O Data Register bit 7
; UCSR0A - USART Control and Status Register A
.equ MPCM0 = 0 ; Multi-processor Communication Mode
.equ U2X0 = 1 ; Double the USART transmission speed
.equ UPE0 = 2 ; Parity Error
.equ DOR0 = 3 ; Data overRun
.equ FE0 = 4 ; Framing Error
.equ UDRE0 = 5 ; USART Data Register Empty
.equ TXC0 = 6 ; USART Transmitt Complete
.equ RXC0 = 7 ; USART Receive Complete
; UCSR0B - USART Control and Status Register B
.equ TXB80 = 0 ; Transmit Data Bit 8
.equ RXB80 = 1 ; Receive Data Bit 8
.equ UCSZ02 = 2 ; Character Size
.equ UCSZ2 = UCSZ02 ; For compatibility
.equ TXEN0 = 3 ; Transmitter Enable
.equ RXEN0 = 4 ; Receiver Enable
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable
; UCSR0C - USART Control and Status Register C
.equ UCPOL0 = 0 ; Clock Polarity
.equ UCSZ00 = 1 ; Character Size
.equ UCSZ01 = 2 ; Character Size
.equ USBS0 = 3 ; Stop Bit Select
.equ UPM00 = 4 ; Parity Mode Bit 0
.equ UPM01 = 5 ; Parity Mode Bit 1
.equ UMSEL0 = 6 ; USART Mode Select
; UBRR0H - USART Baud Rate Register Hight Byte
.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
; UBRR0L - USART Baud Rate Register Low Byte
.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
; ***** USART1 ***********************
; UDR1 - USART I/O Data Register
.equ UDR10 = 0 ; USART I/O Data Register bit 0
.equ UDR11 = 1 ; USART I/O Data Register bit 1
.equ UDR12 = 2 ; USART I/O Data Register bit 2
.equ UDR13 = 3 ; USART I/O Data Register bit 3
.equ UDR14 = 4 ; USART I/O Data Register bit 4
.equ UDR15 = 5 ; USART I/O Data Register bit 5
.equ UDR16 = 6 ; USART I/O Data Register bit 6
.equ UDR17 = 7 ; USART I/O Data Register bit 7
; UCSR1A - USART Control and Status Register A
.equ MPCM1 = 0 ; Multi-processor Communication Mode
.equ U2X1 = 1 ; Double the USART transmission speed
.equ UPE1 = 2 ; Parity Error
.equ DOR1 = 3 ; Data overRun
.equ FE1 = 4 ; Framing Error
.equ UDRE1 = 5 ; USART Data Register Empty
.equ TXC1 = 6 ; USART Transmitt Complete
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