?? m64def.inc
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; ***** PORTF ************************
; PORTF - Data Register, Port F
.equ PORTF0 = 0 ;
.equ PF0 = 0 ; For compatibility
.equ PORTF1 = 1 ;
.equ PF1 = 1 ; For compatibility
.equ PORTF2 = 2 ;
.equ PF2 = 2 ; For compatibility
.equ PORTF3 = 3 ;
.equ PF3 = 3 ; For compatibility
.equ PORTF4 = 4 ;
.equ PF4 = 4 ; For compatibility
.equ PORTF5 = 5 ;
.equ PF5 = 5 ; For compatibility
.equ PORTF6 = 6 ;
.equ PF6 = 6 ; For compatibility
.equ PORTF7 = 7 ;
.equ PF7 = 7 ; For compatibility
; DDRF - Data Direction Register, Port F
.equ DDF0 = 0 ;
.equ DDF1 = 1 ;
.equ DDF2 = 2 ;
.equ DDF3 = 3 ;
.equ DDF4 = 4 ;
.equ DDF5 = 5 ;
.equ DDF6 = 6 ;
.equ DDF7 = 7 ;
; PINF - Input Pins, Port F
.equ PINF0 = 0 ;
.equ PINF1 = 1 ;
.equ PINF2 = 2 ;
.equ PINF3 = 3 ;
.equ PINF4 = 4 ;
.equ PINF5 = 5 ;
.equ PINF6 = 6 ;
.equ PINF7 = 7 ;
; ***** PORTG ************************
; PORTG - Data Register, Port G
.equ PORTG0 = 0 ;
.equ PG0 = 0 ; For compatibility
.equ PORTG1 = 1 ;
.equ PG1 = 1 ; For compatibility
.equ PORTG2 = 2 ;
.equ PG2 = 2 ; For compatibility
.equ PORTG3 = 3 ;
.equ PG3 = 3 ; For compatibility
.equ PORTG4 = 4 ;
.equ PG4 = 4 ; For compatibility
; DDRG - Data Direction Register, Port G
.equ DDG0 = 0 ;
.equ DDG1 = 1 ;
.equ DDG2 = 2 ;
.equ DDG3 = 3 ;
.equ DDG4 = 4 ;
; PING - Input Pins, Port G
.equ PING0 = 0 ;
.equ PING1 = 1 ;
.equ PING2 = 2 ;
.equ PING3 = 3 ;
.equ PING4 = 4 ;
; ***** TIMER_COUNTER_0 **************
; TCCR0 - Timer/Counter Control Register
.equ CS00 = 0 ; Clock Select 0
.equ CS01 = 1 ; Clock Select 1
.equ CS02 = 2 ; Clock Select 2
.equ WGM01 = 3 ; Waveform Generation Mode 1
.equ CTC0 = WGM01 ; For compatibility
.equ COM00 = 4 ; Compare match Output Mode 0
.equ COM01 = 5 ; Compare Match Output Mode 1
.equ WGM00 = 6 ; Waveform Generation Mode 0
.equ PWM0 = WGM00 ; For compatibility
.equ FOC0 = 7 ; Force Output Compare
; TCNT0 - Timer/Counter Register
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0 - Output Compare Register
.equ OCR0_0 = 0 ;
.equ OCR0_1 = 1 ;
.equ OCR0_2 = 2 ;
.equ OCR0_3 = 3 ;
.equ OCR0_4 = 4 ;
.equ OCR0_5 = 5 ;
.equ OCR0_6 = 6 ;
.equ OCR0_7 = 7 ;
; ASSR - Asynchronus Status Register
.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy
.equ OCR0UB = 1 ; Output Compare register 0 Busy
.equ TCN0UB = 2 ; Timer/Counter0 Update Busy
.equ AS0 = 3 ; Asynchronus Timer/Counter 0
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0 = 1 ; Output Compare Flag 0
; SFIOR - Special Function IO Register
;.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
; ETIMSK - Extended Timer/Counter Interrupt Mask Register
.equ OCIE1C = 0 ; Timer/Counter 1, Output Compare Match C Interrupt Enable
; TIFR - Timer/Counter Interrupt Flag register
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
.equ OCF1B = 3 ; Output Compare Flag 1B
.equ OCF1A = 4 ; Output Compare Flag 1A
.equ ICF1 = 5 ; Input Capture Flag 1
; ETIFR - Extended Timer/Counter Interrupt Flag register
.equ OCF1C = 0 ; Timer/Counter 1, Output Compare C Match Flag
; SFIOR - Special Function IO Register
;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
; TCCR1A - Timer/Counter1 Control Register A
.equ WGM10 = 0 ; Waveform Generation Mode Bit 0
.equ PWM10 = WGM10 ; For compatibility
.equ WGM11 = 1 ; Waveform Generation Mode Bit 1
.equ PWM11 = WGM11 ; For compatibility
.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0
.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select bit 0
.equ CS11 = 1 ; Clock Select 1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ WGM12 = 3 ; Waveform Generation Mode
.equ CTC10 = WGM12 ; For compatibility
.equ WGM13 = 4 ; Waveform Generation Mode
.equ CTC11 = WGM13 ; For compatibility
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
; TCCR1C - Timer/Counter1 Control Register C
.equ FOC1C = 5 ; Force Output Compare for channel C
.equ FOC1B = 6 ; Force Output Compare for channel B
.equ FOC1A = 7 ; Force Output Compare for channel A
; ***** TIMER_COUNTER_2 **************
; TCCR2 - Timer/Counter Control Register
.equ CS20 = 0 ; Clock Select
.equ CS21 = 1 ; Clock Select
.equ CS22 = 2 ; Clock Select
.equ WGM21 = 3 ; Waveform Generation Mode
.equ CTC2 = WGM21 ; For compatibility
.equ COM20 = 4 ; Compare Match Output Mode
.equ COM21 = 5 ; Compare Match Output Mode
.equ WGM20 = 6 ; Wafeform Generation Mode
.equ PWM2 = WGM20 ; For compatibility
.equ FOC2 = 7 ; Force Output Compare
; TCNT2 - Timer/Counter Register
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7
; OCR2 - Output Compare Register
.equ OCR2_0 = 0 ; Output Compare Register Bit 0
.equ OCR2_1 = 1 ; Output Compare Register Bit 1
.equ OCR2_2 = 2 ; Output Compare Register Bit 2
.equ OCR2_3 = 3 ; Output Compare Register Bit 3
.equ OCR2_4 = 4 ; Output Compare Register Bit 4
.equ OCR2_5 = 5 ; Output Compare Register Bit 5
.equ OCR2_6 = 6 ; Output Compare Register Bit 6
.equ OCR2_7 = 7 ; Output Compare Register Bit 7
; TIMSK -
.equ TOIE2 = 6 ;
.equ OCIE2 = 7 ;
; TIFR - Timer/Counter Interrupt Flag Register
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
.equ OCF2 = 7 ; Output Compare Flag 2
; ***** TIMER_COUNTER_3 **************
; ETIMSK - Extended Timer/Counter Interrupt Mask Register
.equ OCIE3C = 1 ; Timer/Counter3, Output Compare Match Interrupt Enable
.equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable
.equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable
.equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable
.equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable
; ETIFR - Extended Timer/Counter Interrupt Flag register
.equ OCF3C = 1 ; Timer/Counter3 Output Compare C Match Flag
.equ TOV3 = 2 ; Timer/Counter3 Overflow Flag
.equ OCF3B = 3 ; Output Compare Flag 1B
.equ OCF3A = 4 ; Output Compare Flag 1A
.equ ICF3 = 5 ; Input Capture Flag 1
; SFIOR - Special Function IO Register
;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1
;.equ PSR1 = PSR321 ; For compatibility
;.equ PSR2 = PSR321 ; For compatibility
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
; TCCR3A - Timer/Counter3 Control Register A
.equ WGM30 = 0 ; Waveform Generation Mode Bit 0
.equ PWM30 = WGM30 ; For compatibility
.equ WGM31 = 1 ; Waveform Generation Mode Bit 1
.equ PWM31 = WGM31 ; For compatibility
.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0
.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1
.equ COM3A0 = 6 ; Comparet Ouput Mode 3A, bit 0
.equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1
; TCCR3B - Timer/Counter3 Control Register B
.equ CS30 = 0 ; Clock Select 3 bit 0
.equ CS31 = 1 ; Clock Select 3 bit 1
.equ CS32 = 2 ; Clock Select3 bit 2
.equ WGM32 = 3 ; Waveform Generation Mode
.equ CTC30 = WGM32 ; For compatibility
.equ WGM33 = 4 ; Waveform Generation Mode
.equ CTC31 = WGM33 ; For compatibility
.equ ICES3 = 6 ; Input Capture 3 Edge Select
.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler
; TCCR3C - Timer/Counter3 Control Register C
.equ FOC3C = 5 ; Force Output Compare for channel C
.equ FOC3B = 6 ; Force Output Compare for channel B
.equ FOC3A = 7 ; Force Output Compare for channel A
; TCNT3L - Timer/Counter3 Low Byte
.equ TCN3L0 = 0 ; Timer/Counter 3 bit 0
.equ TCN3L1 = 1 ; Timer/Counter 3 bit 1
.equ TCN3L2 = 2 ; Timer/Counter 3 bit 2
.equ TCN3L3 = 3 ; Timer/Counter 3 bit 3
.equ TCN3L4 = 4 ; Timer/Counter 3 bit 4
.equ TCN3L5 = 5 ; Timer/Counter 3 bit 5
.equ TCN3L6 = 6 ; Timer/Counter 3 bit 6
.equ TCN3L7 = 7 ; Timer/Counter 3 bit 7
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDTCSR = WDTCR ; For compatibility
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDTOE = WDCE ; For compatibility
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lock bit
.equ LB2 = 1 ; Lock bit
.equ BLB01 = 2 ; Boot Lock bit
.equ BLB02 = 3 ; Boot Lock bit
.equ BLB11 = 4 ; Boot lock bit
.equ BLB12 = 5 ; Boot lock bit
; ***** FUSES ************************************************************
; LOW fuse bits
.equ CKSEL0 = 0 ; Select Clock Source
.equ CKSEL1 = 1 ; Select Clock Source
.equ CKSEL2 = 2 ; Select Clock Source
.equ CKSEL3 = 3 ; Select Clock Source
.equ SUT0 = 4 ; Select start-up time
.equ SUT1 = 5 ; Select start-up time
.equ BODEN = 6 ; Brown out detector enable
.equ BODLEVEL = 7 ; Brown out detector trigger level
; HIGH fuse bits
.equ BOOTRST = 0 ; Select Reset Vector
.equ BOOTSZ0 = 1 ; Select Boot Size
.equ BOOTSZ1 = 2 ; Select Boot Size
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
.equ CKOPT = 4 ; Oscillator Options
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
.equ JTAGEN = 6 ; Enable JTAG
.equ OCDEN = 7 ; Enable OCD
; EXTENDED fuse bits
.equ WDTON = 0 ; Watchdog timer always on
.equ CompMode = 1 ; Compabillity mode
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x7fff ; Note: Word address
.equ IOEND = 0x00ff
.equ SRAM_START = 0x0100
.equ SRAM_SIZE = 4096
.equ RAMEND = 0x10ff
.equ XRAMEND = 0xffff
.equ E2END = 0x07ff
.equ EEPROMEND = 0x07ff
.equ EEADRBITS = 11
#pragma AVRPART MEMORY PROG_FLASH 65536
#pragma AVRPART MEMORY EEPROM 2048
#pragma AVRPART MEMORY INT_SRAM SIZE 4096
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
; ***** BOOTLOADER DECLARATIONS ******************************************
.equ NRWW_START_ADDR = 0x7000
.equ NRWW_STOP_ADDR = 0x7fff
.equ RWW_START_ADDR = 0x0
.equ RWW_STOP_ADDR = 0x6fff
.equ PAGESIZE = 128
.equ FIRSTBOOTSTART = 0x7e00
.equ SECONDBOOTSTART = 0x7c00
.equ THIRDBOOTSTART = 0x7800
.equ FOURTHBOOTSTART = 0x7000
.equ SMALLBOOTSTART = FIRSTBOOTSTART
.equ LARGEBOOTSTART = FOURTHBOOTSTART
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0002 ; External Interrupt Request 0
.equ INT1addr = 0x0004 ; External Interrupt Request 1
.equ INT2addr = 0x0006 ; External Interrupt Request 2
.equ INT3addr = 0x0008 ; External Interrupt Request 3
.equ INT4addr = 0x000a ; External Interrupt Request 4
.equ INT5addr = 0x000c ; External Interrupt Request 5
.equ INT6addr = 0x000e ; External Interrupt Request 6
.equ INT7addr = 0x0010 ; External Interrupt Request 7
.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match
.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow
.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event
.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x001a ; Timer/Counter Compare Match B
.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow
.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match
.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete
.equ URXC0addr = 0x0024 ; USART0, Rx Complete
.equ UDRE0addr = 0x0026 ; USART0 Data Register Empty
.equ UTXC0addr = 0x0028 ; USART0, Tx Complete
.equ ADCCaddr = 0x002a ; ADC Conversion Complete
.equ ERDYaddr = 0x002c ; EEPROM Ready
.equ ACIaddr = 0x002e ; Analog Comparator
.equ OC1Caddr = 0x0030 ; Timer/Counter1 Compare Match C
.equ ICP3addr = 0x0032 ; Timer/Counter3 Capture Event
.equ OC3Aaddr = 0x0034 ; Timer/Counter3 Compare Match A
.equ OC3Baddr = 0x0036 ; Timer/Counter3 Compare Match B
.equ OC3Caddr = 0x0038 ; Timer/Counter3 Compare Match C
.equ OVF3addr = 0x003a ; Timer/Counter3 Overflow
.equ URXC1addr = 0x003c ; USART1, Rx Complete
.equ UDRE1addr = 0x003e ; USART1, Data Register Empty
.equ UTXC1addr = 0x0040 ; USART1, Tx Complete
.equ TWIaddr = 0x0042 ; 2-wire Serial Interface
.equ SPMRaddr = 0x0044 ; Store Program Memory Read
.equ INT_VECTORS_SIZE = 70 ; size in words
#endif /* _M64DEF_INC_ */
; ***** END OF FILE ******************************************************
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